From patchwork Fri Apr 3 09:33:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 6155071 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2430CBF4A6 for ; Fri, 3 Apr 2015 09:34:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 31431203DC for ; Fri, 3 Apr 2015 09:34:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3B094201DD for ; Fri, 3 Apr 2015 09:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752339AbbDCJeL (ORCPT ); Fri, 3 Apr 2015 05:34:11 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:18615 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752348AbbDCJeH (ORCPT ); Fri, 3 Apr 2015 05:34:07 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NM800AQF5FDM400@mailout4.w1.samsung.com>; Fri, 03 Apr 2015 10:38:01 +0100 (BST) X-AuditID: cbfec7f5-b7fc86d0000066b7-af-551e5de0a999 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id E9.DD.26295.0ED5E155; Fri, 03 Apr 2015 10:31:12 +0100 (BST) Received: from AMDC1943.digital.local ([106.116.151.171]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NM800H5O58NCL70@eusync2.samsung.com>; Fri, 03 Apr 2015 10:34:04 +0100 (BST) From: Krzysztof Kozlowski To: Andrzej Hajda , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Kukjin Kim Cc: Marek Szyprowski , Javier Martinez Canillas , Krzysztof Kozlowski Subject: [PATCH v2 1/2] ARM: EXYNOS: Get current parent clock for power domain on/off Date: Fri, 03 Apr 2015 11:33:54 +0200 Message-id: <1428053635-10855-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCJMWRmVeSWpSXmKPExsVy+t/xK7oPYuVCDea9VbC4te4cq8X8I0Di 6O8Ci9cvDC36H79mttj0+BqrxeVdc9gsZpzfx2Sx9shddgdOj7/Pr7N4bFrVyeaxeUm9R9+W VYwenzfJBbBGcdmkpOZklqUW6dslcGVs/POJqaBTvOLK868sDYwPhboYOTkkBEwkFvTfYYKw xSQu3FvP1sXIxSEksJRRonXjURYIp49JYvfWM8wgVWwCxhKbly8BqxIROMsosXb2fiYQh1lg HqPE4S33gFo4OIQFwiWmHDEEMVkEVCUevswEMXkF3CV2vs6DWCYncfLYZNYJjNwLGBlWMYqm liYXFCel5xrpFSfmFpfmpesl5+duYoSEzNcdjEuPWR1iFOBgVOLhtSiWDRViTSwrrsw9xCjB wawkwpseIhcqxJuSWFmVWpQfX1Sak1p8iJGJg1OqgXHa3b65DclSNypzn5XM+zXV8aeMc+TN PyYGr9KfrH0dseGDssjueBtFRttznZfaX5VtqPFVuf138bqEg9mqp5vPrly3gn/XlYAPWYtW NN1QWvn0kduPs1c2vFH62uyYLTHb+vI3F1+WG0o1Xn0fOzOTExeznSmwnHOj46XAueVdnm2t jMxcKlFKLMUZiYZazEXFiQAC/vIu9wEAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using a fixed (by DTS) parent for clocks when turning on the power domain may introduce issues in other drivers. For example when such driver changes the parent during runtime and expects that he is the only place of such change. Do not rely on DTS providing the fixed parent for such clocks. Instead before switching domain off, grab a current parent of a clock with clk_get_parent(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- Changes since v1: 1. Drop "pclk" bindings entirely as suggested by Andrzej Hajda. This was significant change so I did not add Javier's reviewed/tested tags. --- Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 7 ++++--- arch/arm/mach-exynos/pm_domains.c | 9 ++------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 5da38c5ed476..e151057d92f0 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -19,9 +19,10 @@ Optional Properties: domains. - clock-names: The following clocks can be specified: - oscclk: Oscillator clock. - - pclkN, clkN: Pairs of parent of input clock and input clock to the - devices in this power domain. Maximum of 4 pairs (N = 0 to 3) - are supported currently. + - clkN: Input clocks to the devices in this power domain. These clocks + will be reparented to oscclk before swithing power domain off. + Their original parent will be brought back after turning on + the domain. Maximum of 4 clocks (N = 0 to 3) are supported. - asbN: Clocks required by asynchronous bridges (ASB) present in the power domain. These clock should be enabled during power domain on/off operations. diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index cbe56b35aea0..056e0a09f381 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -62,6 +62,7 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; + pd->pclk[i] = clk_get_parent(pd->clk[i]); if (clk_set_parent(pd->clk[i], pd->oscclk)) pr_err("%s: error setting oscclk as parent to clock %d\n", pd->name, i); @@ -161,13 +162,7 @@ static __init int exynos4_pm_init_power_domain(void) pd->clk[i] = clk_get(dev, clk_name); if (IS_ERR(pd->clk[i])) break; - snprintf(clk_name, sizeof(clk_name), "pclk%d", i); - pd->pclk[i] = clk_get(dev, clk_name); - if (IS_ERR(pd->pclk[i])) { - clk_put(pd->clk[i]); - pd->clk[i] = ERR_PTR(-EINVAL); - break; - } + pd->pclk[i] = clk_get_parent(pd->clk[i]); } if (IS_ERR(pd->clk[0]))