From patchwork Fri May 8 11:07:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 6364171 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2890C9F32B for ; Fri, 8 May 2015 11:08:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3690520204 for ; Fri, 8 May 2015 11:08:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38282201C8 for ; Fri, 8 May 2015 11:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752220AbbEHLIp (ORCPT ); Fri, 8 May 2015 07:08:45 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:34312 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751751AbbEHLIo (ORCPT ); Fri, 8 May 2015 07:08:44 -0400 Received: by pdbqa5 with SMTP id qa5so76315086pdb.1; Fri, 08 May 2015 04:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=tLmvKONQtB8iTwfbxzBrzh0vOPjrBQjqdYhgfcC/XZs=; b=F6SJhK0xCmM8L7dS1Ey00pZeP/fk2GGhuZA16K03JSQFxbWRIL6C9pOhu1CjUeNV+U rIH8wamftBzHpkPJexDbaO96EaSsA1D9UgSjpJ/tVi7rY2eRzjnJH1UlPtEBQQOKpnW4 k+UOsgBFUJK5sAWaAekL9x44yNjpA/xI/9OArORSakviPIIfXrVAZvewoUFoH6LdLpSQ fVLNbrwvcNUE09SZSLw1CQ1juseeJFqnDSLt2rBas2ApJUKM8QV1Lzfe1Og8a1jU2Sos S3fc5IMc2WaltDc7FMym58j07BgaEW1VShJ4HdHrj7bwgsn999tD8asCAFzW+C/+eVXY nOQg== X-Received: by 10.67.3.195 with SMTP id by3mr5555478pad.109.1431083296107; Fri, 08 May 2015 04:08:16 -0700 (PDT) Received: from localhost.localdomain ([110.227.55.149]) by mx.google.com with ESMTPSA id nw8sm4892034pdb.30.2015.05.08.04.07.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 May 2015 04:08:14 -0700 (PDT) From: Anand Moon To: Bartlomiej Zolnierkiewicz , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Stephen Boyd , Kukjin Kim Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Anand Moon Subject: [PATCHv3] clk samsung exynos5420 add CLK_RECALC_NEW_RATES flag to mout_apll and mout_kpll clock. Date: Fri, 8 May 2015 20:37:27 +0930 Message-Id: <1431083247-3310-1-git-send-email-linux.amoon@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Addition of CLK_RECALC_NEW_RATES flag to support Exynos5420 cpu clk so that correct divider values are re-calculated after both pre/post clock notifiers had run for mout_apll clock and mout_kpll clock. Observation their is considerable improvement in cpufreq stats after applying this patch. Governer : "performance" $ cpupower -c 1 frequency-info Below is table format of the output. cpufreq stats: Frequency| Before | After | CPU 1 200 MHz | 22.07% | 46.57% | 300 MHz | 1.08% | 8.18% | 400 MHz | 0.17% | 1.93% | 500 MHz | 0.24% | 3.51% | 600 MHz | 0.37% | 2.13% | 700 MHz | 0.20% | 0.88% | 800 MHz | 0.09% | 1.69% | 900 MHz | 0.05% | 1.02% | 1000 MHz | 0.02% | 2.55% | 1.10 GHz | 0.12% | 1.17% | 1.20 GHz | 0.05% | 0.88% | 1.30 GHz | 0.07% | 0.38% | 1.40 GHz | 0.04% | 0.38% | 1.50 GHz | 0.02% | 0.00% | 1.60 GHz | 0.00% | 0.15% | 1.70 GHz | 0.00% | 0.44% | 1.80 GHz | 75.43% | 28.26% | Governer : "performance" $ cpupower -c 0 frequency-info Below is table format of the output. cpufreq stats: Frequency| Before | After | CPU0 200 MHz | 33.95% | 60.31% | 300 MHz | 4.64% | 2.13% | 400 MHz | 1.50% | 0.79% | 500 MHz | 1.46% | 0.49% | 600 MHz | 0.05% | 0.27% | 700 MHz | 0.68% | 0.21% | 800 MHz | 0.08% | 0.19% | 900 MHz | 0.09% | 0.12% | 1000 MHz | 0.20% | 0.10% | 1.10 GHz | 0.21% | 0.11%, | 1.20 GHz | 0.51% | 0.28%, | 1.30 GHz | 56.64% | 35.01% | Reviewed-by: Krzysztof Kozlowski Signed-off-by: Anand Moon --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 462aaee..6c7458c 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -618,10 +618,10 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0), + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, - CLK_SET_RATE_PARENT, 0), + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),