From patchwork Sun May 31 14:34:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 6516061 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2ED05C0433 for ; Sun, 31 May 2015 14:34:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 407682061A for ; Sun, 31 May 2015 14:34:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3DF912061D for ; Sun, 31 May 2015 14:34:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758252AbbEaOek (ORCPT ); Sun, 31 May 2015 10:34:40 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:36507 "EHLO mail-pd0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758123AbbEaOej (ORCPT ); Sun, 31 May 2015 10:34:39 -0400 Received: by pdjm12 with SMTP id m12so5989467pdj.3 for ; Sun, 31 May 2015 07:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=107q7EMlfGfiaK7RJxxEL2vSmXyV7LXJ1Ds6r7lMC50=; b=0/euQxfe79tiJxRuwkKXqtXe/HYXcux+fmMxq5GxHiEM/0TFtQ8NMyfr6wEE0c7dR3 9uwOGUNXC2KRazYebd6xHf7f+9cMA918Oi2Zsav+Mc02r+2oWjhxKaudd2mj95vXSl03 8rfp3NMvgd+kqGjFjzWXtHHHmUmxz6yPDtpokYM5mcqq5Pz7azL0GBmuA2P648UnhDcm lR5SYlXV1L277+NnK0Vu3w5SznWz3OcqH7fleZSMoUk7jqwdeLfEEFdQivYnhY7Qg2IH Wr+1OfektlL6+JyI6zowdOUY9Y4r0nFJpI1l/z+Smo1AbNSp7AYRdXsDjb4iI7mETfAS VcGQ== X-Received: by 10.68.167.131 with SMTP id zo3mr32032769pbb.123.1433082878987; Sun, 31 May 2015 07:34:38 -0700 (PDT) Received: from localhost.localdomain ([182.225.40.2]) by mx.google.com with ESMTPSA id c8sm11457074pdj.65.2015.05.31.07.34.35 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 31 May 2015 07:34:38 -0700 (PDT) From: Chanho Park X-Google-Original-From: Chanho Park To: kgene@kernel.org, k.kozlowski@samsung.com Cc: jy0922.shim@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, javier.martinez@collabora.co.uk, khilman@linaro.org, sjoerd.simons@collabora.co.uk, heesub.shin@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Chanho Park Subject: [PATCHv2] ARM: dts: add exynos5422-cpus.dtsi to correct cpu order Date: Sun, 31 May 2015 23:34:27 +0900 Message-Id: <1433082867-32359-1-git-send-email-chanho61.park@samsung.com> X-Mailer: git-send-email 2.1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Signed-off-by: Chanho Park --- Changes from v1: - rename exynos5422.dtsi to exynos5422-cpus.dtsi - include the dtsi file top of the exynos5422-odroidxu3.dts arch/arm/boot/dts/exynos5422-cpus.dtsi | 88 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 +- 2 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 0000000..d39db49 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,88 @@ +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file to provide cpu ordering + * which could boot a cortex-a7 from cpu0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos5420.dtsi" + +/ { + compatible = "samsung,exynos5800", "samsung,exynos5422", + "samsung,exynos5"; +}; + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index edc25cf..00f45c9 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -12,10 +12,12 @@ /dts-v1/; #include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" / { model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", + "samsung,exynos5422", "samsung,exynos5"; memory { reg = <0x40000000 0x7EA00000>;