From patchwork Mon Jun 1 10:10:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 6520351 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EE473C0433 for ; Mon, 1 Jun 2015 10:11:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6293205E2 for ; Mon, 1 Jun 2015 10:11:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95A51205F0 for ; Mon, 1 Jun 2015 10:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752542AbbFAKLc (ORCPT ); Mon, 1 Jun 2015 06:11:32 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:17060 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752589AbbFAKL3 (ORCPT ); Mon, 1 Jun 2015 06:11:29 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NP900I57GB25F20@mailout1.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 01 Jun 2015 11:11:27 +0100 (BST) X-AuditID: cbfec7f4-f79c56d0000012ee-68-556c2fce628a Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id BB.DA.04846.ECF2C655; Mon, 1 Jun 2015 11:11:26 +0100 (BST) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NP9008Z3GAUIW80@eusync1.samsung.com>; Mon, 01 Jun 2015 11:11:26 +0100 (BST) From: Marek Szyprowski To: iommu@lists.linux-foundation.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Szyprowski , Inki Dae , Kukjin Kim , Joonyoung Shim , Seung-Woo Kim , Javier Martinez Canillas , Krzysztof Kozlowski , Krzysztof Kozlowski Subject: [PATCH 6/6] ARM: dts: exynos5420: add sysmmu nodes Date: Mon, 01 Jun 2015 12:10:50 +0200 Message-id: <1433153450-3680-7-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1433153450-3680-1-git-send-email-m.szyprowski@samsung.com> References: <1432041645-11172-1-git-send-email-m.szyprowski@samsung.com> <1433153450-3680-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrILMWRmVeSWpSXmKPExsVy+t/xy7rn9HNCDSZNMbaYdH8Ci8WC/dYW 137PYLN4ce8ii8Xzfz/YLV6/MLTof/ya2WLT42usFjPO72OyWHvkLrvFjMkv2Ry4Pf7ObmX2 2DnrLrvHplWdbB6bl9R7TL6xnNGjb8sqRo/Pm+QC2KO4bFJSczLLUov07RK4Mg4u/spcsMOy 4tCyl0wNjF16XYycHBICJhI7e7uYIWwxiQv31rN1MXJxCAksZZT4uLeNFcJpYpK4eWYjO0gV m4ChRNfbLjYQW0QgX+LF3r8sIEXMAreZJOZuXgs2SljAWuLU3kawIhYBVYn35xezgNi8Au4S myeuZ4FYJyfx/+UKJhCbU8BD4uLRGVDb2hglbuy9xz6BkXcBI8MqRtHU0uSC4qT0XEO94sTc 4tK8dL3k/NxNjJCA/LKDcfExq0OMAhyMSjy8Ap3ZoUKsiWXFlbmHGCU4mJVEeFOkc0KFeFMS K6tSi/Lji0pzUosPMUpzsCiJ887d9T5ESCA9sSQ1OzW1ILUIJsvEwSnVwJjS4qzKqquuddO+ Te6utF0jh5ngyTz+WPNjdlzvLryQ3Gjxb5XHRKUXIdOFPxUv6hQ5kFP6//9Xx/aiB0s3Hpn1 /0P6iojJsetlVkxQ9VoT68Yc8qqhrvyN36b1b49FzWX89ydXI95wvbzwgpVyaSmsF2et3Lvz QrBr3Vfe9IDiOofpQgriYUosxRmJhlrMRcWJABK3j6REAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds System MMU nodes to all defined devices that are specific to Exynos5420/5800/5422 series. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 183 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d0be412dfbea..534f27ceb10b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -179,6 +179,8 @@ clocks = <&clock CLK_MFC>; clock-names = "mfc"; power-domains = <&mfc_pd>; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; }; mmc_0: mmc@12200000 { @@ -713,6 +715,7 @@ <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "hdmi", "sclk_hdmi"; power-domains = <&disp_pd>; + iommus = <&sysmmu_tv>; }; gsc_0: video-scaler@13e00000 { @@ -722,6 +725,7 @@ clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl0>; }; gsc_1: video-scaler@13e10000 { @@ -731,6 +735,7 @@ clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; power-domains = <&gsc_pd>; + iommus = <&sysmmu_gscl1>; }; jpeg_0: jpeg@11F50000 { @@ -739,6 +744,7 @@ interrupts = <0 89 0>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; + iommus = <&sysmmu_jpeg0>; }; jpeg_1: jpeg@11F60000 { @@ -747,6 +753,7 @@ interrupts = <0 168 0>; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; + iommus = <&sysmmu_jpeg1>; }; pmu_system_controller: system-controller@10040000 { @@ -941,6 +948,180 @@ samsung,sysreg-phandle = <&sysreg_system_controller>; samsung,pmureg-phandle = <&pmu_system_controller>; }; + + sysmmu_g2dr: sysmmu@0x10A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_g2dw: sysmmu@0x10A70000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10A70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_tv: sysmmu@0x14650000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl0: sysmmu@0x13E80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_gscl1: sysmmu@0x13E90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + power-domains = <&gsc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0r: sysmmu@0x12880000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1r: sysmmu@0x12890000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12890000 0x1000>; + interrupts = <0 186 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2r: sysmmu@0x128A0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128A0000 0x1000>; + interrupts = <0 188 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_scaler0w: sysmmu@0x128C0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + #iommu-cells = <0>; + }; + + sysmmu_scaler1w: sysmmu@0x128D0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + #iommu-cells = <0>; + }; + + sysmmu_scaler2w: sysmmu@0x128E0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x128E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg0: sysmmu@0x11F10000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + #iommu-cells = <0>; + }; + + sysmmu_jpeg1: sysmmu@0x11F20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11F20000 0x1000>; + interrupts = <0 169 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_l: sysmmu@0x11200000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_mfc_r: sysmmu@0x11210000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + power-domains = <&mfc_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_0: sysmmu@0x14640000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; + + sysmmu_fimd1_1: sysmmu@0x14680000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + power-domains = <&disp_pd>; + #iommu-cells = <0>; + }; }; &dp { @@ -955,6 +1136,8 @@ clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; power-domains = <&disp_pd>; + iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; + iommu-names = "m0", "m1"; }; &rtc {