From patchwork Mon Jun 1 12:24:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 6521471 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E6E16C0020 for ; Mon, 1 Jun 2015 12:24:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02E1B205FA for ; Mon, 1 Jun 2015 12:24:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C296520605 for ; Mon, 1 Jun 2015 12:24:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751234AbbFAMYf (ORCPT ); Mon, 1 Jun 2015 08:24:35 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:36607 "EHLO mail-pd0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751750AbbFAMYe (ORCPT ); Mon, 1 Jun 2015 08:24:34 -0400 Received: by pdjm12 with SMTP id m12so23713585pdj.3 for ; Mon, 01 Jun 2015 05:24:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=eQzztLuUeL+9X3wkOOMW5ONyc7gipBk+lf2DXa+sXIY=; b=a7z3XAajF+iqA7knndGcP0NxzJWZI0p3X3kaAbTMPxrrsxHSuKkpZLof9XiS4Yqnal gEsMEZjYF97aNy3hyCAk02vbG8bbr4btrnexQ6ZNXvMj+HZHFHU3hkCfe38yEb1Id+wF ux+5alhS9crX7hAiSifxibEfMQ3Rf6gErF/hJ9emYwdJFhHE53uiT1VLImYyM1UVwv2U ZFaX53JabD0Xn+u5lXSPhM3RF0yYluk5DXQVY521bB0m9LlBGR7JfsmUbRCS6lIQyGrZ 7W1XdoTIkGMAjMp07NkbTEp5p/DKGMr5H3x6fr+u6ZZUMbU6hj2tbeLhqqCgZMD9NHoj E9wQ== X-Received: by 10.68.113.194 with SMTP id ja2mr2591922pbb.163.1433161474067; Mon, 01 Jun 2015 05:24:34 -0700 (PDT) Received: from localhost.localdomain ([182.225.40.2]) by mx.google.com with ESMTPSA id jp10sm14127146pbb.9.2015.06.01.05.24.29 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Jun 2015 05:24:33 -0700 (PDT) From: Chanho Park X-Google-Original-From: Chanho Park To: kgene@kernel.org, k.kozlowski@samsung.com Cc: jy0922.shim@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, javier.martinez@collabora.co.uk, khilman@linaro.org, sjoerd.simons@collabora.co.uk, heesub.shin@samsung.com, m.szyprowski@samsung.com, b.zolnierkie@samsung.com, Chanho Park Subject: [PATCHv3] ARM: dts: add exynos5422-cpus.dtsi to correct cpu order Date: Mon, 1 Jun 2015 21:24:19 +0900 Message-Id: <1433161459-10901-1-git-send-email-chanho61.park@samsung.com> X-Mailer: git-send-email 2.1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski --- Change from v2: - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi - drop compatibles from exynos5422-cpus.dtsi Changes from v1: - rename exynos5422.dtsi to exynos5422-cpus.dtsi - include the dtsi file top of the exynos5422-odroidxu3.dts arch/arm/boot/dts/exynos5422-cpus.dtsi | 81 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 +- 2 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 0000000..b7f60c8 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,81 @@ +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file to provide cpu ordering + * which could boot a cortex-a7 from cpu0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index edc25cf..00f45c9 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -12,10 +12,12 @@ /dts-v1/; #include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" / { model = "Hardkernel Odroid XU3"; - compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", + "samsung,exynos5422", "samsung,exynos5"; memory { reg = <0x40000000 0x7EA00000>;