From patchwork Thu Jun 11 08:26:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 6586441 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7D78A9F326 for ; Thu, 11 Jun 2015 08:26:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7DE2720648 for ; Thu, 11 Jun 2015 08:26:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5A5A2063C for ; Thu, 11 Jun 2015 08:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751090AbbFKI0x (ORCPT ); Thu, 11 Jun 2015 04:26:53 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:15409 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750825AbbFKI0u (ORCPT ); Thu, 11 Jun 2015 04:26:50 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NPR00EHVU4N3V90@mailout2.w1.samsung.com>; Thu, 11 Jun 2015 09:26:47 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-7d-557946461a5a Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id AE.FE.05269.64649755; Thu, 11 Jun 2015 09:26:46 +0100 (BST) Received: from localhost.localdomain ([10.252.80.64]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NPR00D3CU4C6210@eusync1.samsung.com>; Thu, 11 Jun 2015 09:26:46 +0100 (BST) From: Krzysztof Kozlowski To: Kukjin Kim , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Stephen Boyd , Marek Szyprowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] clk: exynos4: Add PCLK_ADC gate clock on Exynos4x12 Date: Thu, 11 Jun 2015 17:26:29 +0900 Message-id: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLLMWRmVeSWpSXmKPExsVy+t/xy7pubpWhBlt/WVrMP3KO1eL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2Sx9shddounEy6yWRx+085q8eNMN4vFql1/GB14 PC739TJ57Jx1l91j06pONo871/aweWxeUu/Rt2UVo8fnTXIB7FFcNimpOZllqUX6dglcGS17 HAv28Va0zOtma2Dcxt3FyMkhIWAicWXCXVYIW0ziwr31bF2MXBxCAksZJY4/ecYC4fxnlNg9 aQoTSBWbgLHE5uVLwKpEBKYySyz/ehkswSxgKPHz3R92EFtYwENiS1s7G4jNIqAq0f9tP9gK XgF3ib9TW5gg1slJnDw2mXUCI/cCRoZVjKKppckFxUnpuUZ6xYm5xaV56XrJ+bmbGCGB9nUH 49JjVocYBTgYlXh4K05UhAqxJpYVV+YeYpTgYFYS4Y02qQwV4k1JrKxKLcqPLyrNSS0+xCjN waIkzjtz1/sQIYH0xJLU7NTUgtQimCwTB6dUA2Nf3IYyWQkXjhVK7p/cDytK1gSX9f532vJA X11sypklC478fRm/xjIsKdbCTeaGG89DXm45s7lmf4OuTcpYriJ4L9EmY/Oapt0Za5tsdi3q 3hB3bs33+tLW4qCCycfPcEyYd2mCZ+zOGB9VrweSiXpGd02P/vmc42eW2rbUPeOTbsfbx5bh fUosxRmJhlrMRcWJAMB9AzswAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add proper gate clock for the Analog to Digital Converter (ADC) on Exynos4x12. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 3 +++ include/dt-bindings/clock/exynos4.h | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 714d6ba782c8..5f32410a01f8 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -85,6 +85,7 @@ #define DIV_PERIL4 0xc560 #define DIV_PERIL5 0xc564 #define E4X12_DIV_CAM1 0xc568 +#define E4X12_GATE_BUS_FSYS1 0xc744 #define GATE_SCLK_CAM 0xc820 #define GATE_IP_CAM 0xc920 #define GATE_IP_TV 0xc924 @@ -1095,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, 0), + GATE(CLK_PCLK_ADC, "pclk_adc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, + 0), GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index c4b1676ea674..4548531736c1 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -268,7 +268,10 @@ #define CLK_DIV_GDL 459 #define CLK_DIV_GDR 460 +/* Exynos4x12 only */ +#define CLK_PCLK_ADC 461 + /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 461 +#define CLK_NR_CLKS 462 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */