From patchwork Fri Jun 12 01:53:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 6593831 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A56FC0020 for ; Fri, 12 Jun 2015 01:54:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6A1220650 for ; Fri, 12 Jun 2015 01:54:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD95E20212 for ; Fri, 12 Jun 2015 01:54:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751155AbbFLBxq (ORCPT ); Thu, 11 Jun 2015 21:53:46 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:50784 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbbFLBxo (ORCPT ); Thu, 11 Jun 2015 21:53:44 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NPT00KWN6LHA610@mailout3.w1.samsung.com>; Fri, 12 Jun 2015 02:53:41 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-25-557a3ba4378d Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id BA.3C.05269.4AB3A755; Fri, 12 Jun 2015 02:53:40 +0100 (BST) Received: from localhost.localdomain ([10.252.80.64]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NPT00GNS6L93E30@eusync2.samsung.com>; Fri, 12 Jun 2015 02:53:40 +0100 (BST) From: Krzysztof Kozlowski To: Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Javier Martinez Canillas , stable@vger.kernel.org Subject: [PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC Date: Fri, 12 Jun 2015 10:53:25 +0900 Message-id: <1434074005-18846-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrELMWRmVeSWpSXmKPExsVy+t/xK7pLrKtCDc73GFhc+z2DzeL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2TxdMJFNovDb9pZLX6c6WaxWLDxEaPFql1/GB14 PC739TJ5/J3dyuyxc9Zddo9NqzrZPO5c28PmsXlJvUffllWMHp83yQVwRHHZpKTmZJalFunb JXBl7Do9gb3gv3DF0e2n2BoYzwh0MXJySAiYSKxZ9IsZwhaTuHBvPVsXIxeHkMBSRolnE7cx QTj/GSUunv/BAlLFJmAssXn5ErAqEYHfTBJ/P18Ea2cW8JJ4PfMLWJGwgIvEz/bnQDYHB4uA qsSOLyogYV4Bd4kd89ayQGyTkzh5bDLrBEbuBYwMqxhFU0uTC4qT0nON9IoTc4tL89L1kvNz NzFCQu7rDsalx6wOMQpwMCrx8CZoVYUKsSaWFVfmHmKU4GBWEuH9owAU4k1JrKxKLcqPLyrN SS0+xCjNwaIkzjtz1/sQIYH0xJLU7NTUgtQimCwTB6dUAyNjesDcP8qV96593XlgeudFrspG a/slhxdF6K5lrPs67f7JaddePDvgNMvhyM1JMvv2pl25K7Dnv1La2S0RJ9NTTkkfSUuqOlkp tnd5waeH4d+qt2yb67X8dyrHItfS265WnIEb6zZ73bDc77KUa2+RaZ7/C709SnM+7Px4zW7n Ft9lv5b+td6TqMRSnJFoqMVcVJwIAHBZS1g1AgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver. However TSADC is present only on Exynos4210 so on Trats2 board (with Exynos4412 SoC) the exynos-adc driver could not be probed: ERROR: could not get clock /adc@126C0000:adc(0) exynos-adc 126c0000.adc: failed getting clock, err = -2 exynos-adc: probe of 126c0000.adc failed with error -2 Instead on Exynos4x12 SoCs the main clock used by Analog to Digital Converter is located in different register and it is named in datasheet as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock is the same as purpose of TSADC from Exynos4210. The patch adds gate clock for Exynos4x12 using the proper register so backward compatibility is preserved. This fixes the probe of exynos-adc driver on Exynos4x12 boards and allows accessing sensors connected to it on Trats2 board (ntc,ncp15wb473 AP and battery thermistors). Signed-off-by: Krzysztof Kozlowski Cc: Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12") Link: https://lkml.org/lkml/2015/6/11/85 Reviewed-by: Javier Martinez Canillas Acked-by: Tomasz Figa --- Changes since v1: 1. After discussion on LKML this solution was chosen because it smaller, simpler, self-contained (one patch to fix issue) and maintains backward compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for valuable comments. 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC" will be used on all Exynos4 boards. 3. Added CC-stable. --- drivers/clk/samsung/clk-exynos4.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 714d6ba782c8..f7890bf652e6 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -85,6 +85,7 @@ #define DIV_PERIL4 0xc560 #define DIV_PERIL5 0xc564 #define E4X12_DIV_CAM1 0xc568 +#define E4X12_GATE_BUS_FSYS1 0xc744 #define GATE_SCLK_CAM 0xc820 #define GATE_IP_CAM 0xc920 #define GATE_IP_TV 0xc924 @@ -1095,6 +1096,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 0), GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, 0), + GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0), GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,