From patchwork Mon Jun 29 17:26:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 6690591 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 92F519F380 for ; Mon, 29 Jun 2015 17:29:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8F96D205C4 for ; Mon, 29 Jun 2015 17:29:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72F4320465 for ; Mon, 29 Jun 2015 17:29:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753433AbbF2R2X (ORCPT ); Mon, 29 Jun 2015 13:28:23 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:46749 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751464AbbF2R2K (ORCPT ); Mon, 29 Jun 2015 13:28:10 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NQP01SYGV6WIX10@mailout3.samsung.com>; Tue, 30 Jun 2015 02:28:08 +0900 (KST) X-AuditID: cbfee61a-f79516d000006302-74-5591802852ae Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 04.B6.25346.82081955; Tue, 30 Jun 2015 02:28:08 +0900 (KST) Received: from AMDC1976.DIGITAL.local ([106.120.53.102]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NQP0081NV60N630@mmp1.samsung.com>; Tue, 30 Jun 2015 02:28:07 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Michael Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com, Mike Turquette Subject: [PATCH v2 1/4] clk: samsung: exynos5250: add cpu clock configuration data and instantiate cpu clock Date: Mon, 29 Jun 2015 19:26:09 +0200 Message-id: <1435598772-21708-2-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1435598772-21708-1-git-send-email-b.zolnierkie@samsung.com> References: <1435598772-21708-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRmVeSWpSXmKPExsVy+t9jAV2NhomhBgd281tsnLGe1eL6l+es Fv8fvWa1OPq7wOL1C0OL3gVX2Sz6H79mtvh6eAWjxZuHmxktNj2+xmrxseceq8XlXXPYLD73 HmG0mHF+H5PFxVOuFk8nXGSzOPymndWiYxmjxapdfxgtNn71cBDxeH+jld3j7/PrLB47Z91l 99i0qpPN4861PWwem5fUe/RtWcXosf3aPGaPz5vkAjijuGxSUnMyy1KL9O0SuDKWTVjNXLBT rmLC913sDYwrJbsYOTkkBEwkvj5dwAphi0lcuLeeDcQWEljEKDH1dkIXIxeQ/YtR4tyHF+wg CTYBK4mJ7asYQRIiAiuYJKY/2ccO4jALPGGW2LdkGyNIlbBAnsSP231MXYwcHCwCqhJ/Z3CD hHkFPCSWHVwDtU1O4uSxyWA2p4CnxIbXp6A2e0h0/+5lmcDIu4CRYRWjaGpBckFxUnquoV5x Ym5xaV66XnJ+7iZGcNA/k9rBuLLB4hCjAAejEg+vx/sJoUKsiWXFlbmHGCU4mJVEeJliJ4YK 8aYkVlalFuXHF5XmpBYfYpTmYFES5z2Z7xMqJJCeWJKanZpakFoEk2Xi4JRqYOQtn2MzL+Aq O7ee/mHv77bChT6f9xddLpHdObOPc4FLqcXBVXt8Z3rdjO5V7TI80HHLof1mqOZx34bm7Yf6 r8xqW+dfssXxy8TcLbM2y37bd/po3iZGVWMNxegdVTYLVBOKXk3izhb3nyuSmXjXty15enRB jv28imQHJZZdjswz/thWq2z8qsRSnJFoqMVcVJwIAPsO+wF2AgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Changes by Bartlomiej: - split Exynos5250 support from the original patch - moved E5250_CPU_DIV[0,1]() macros to clk-exynos5250.c Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Signed-off-by: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/clk/samsung/clk-exynos5250.c | 31 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos5250.h | 1 + 2 files changed, 32 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 70ec3d2..d87f34d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -748,6 +749,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { VPLL_LOCK, VPLL_CON0, NULL), }; +#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \ + ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((periph) << 12) | ((acp) << 8) | ((cpud) << 4))) +#define E5250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | (copy)) + +static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { + { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 0 }, +}; + static const struct of_device_id ext_clk_match[] __initconst = { { .compatible = "samsung,clock-xxti", .data = (void *)0, }, { }, @@ -797,6 +824,10 @@ static void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks)); samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d), + CLK_CPU_HAS_DIV1); /* * Enable arm clock down (in idle) and set arm divider diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 4273891d..8183d1c 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -21,6 +21,7 @@ #define CLK_FOUT_CPLL 6 #define CLK_FOUT_EPLL 7 #define CLK_FOUT_VPLL 8 +#define CLK_ARM_CLK 9 /* gate for special clocks (sclk) */ #define CLK_SCLK_CAM_BAYER 128