From patchwork Mon Jul 6 14:12:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 6724531 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 96CCEC05AC for ; Mon, 6 Jul 2015 14:13:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4B442041C for ; Mon, 6 Jul 2015 14:13:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9041D2050B for ; Mon, 6 Jul 2015 14:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756594AbbGFOM7 (ORCPT ); Mon, 6 Jul 2015 10:12:59 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:32783 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756173AbbGFOM4 (ORCPT ); Mon, 6 Jul 2015 10:12:56 -0400 Received: by pacws9 with SMTP id ws9so97601641pac.0 for ; Mon, 06 Jul 2015 07:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=V1MuWtu1XpntvUuVvJDsD2H6doe0qOMu/jJRerws2tA=; b=OJSgxaMKNUYgm7GO0CGk1lY0hSuNhKS7RmJ9FeO+1VrmpmQNiHa0TuaVIAL+n2y7z9 NG8xLdsSpYgW2y60T3q8Rw80idvvcpb6e258t8vWIl020tx6QtjUlIrXf37v3ArBjrK/ KZRZAtLx5unB5XKcRU/yJfi+c7R4NTX5krEwbAQCi1F3ePmppztI7KRT0sVsx3qYX2nW w79uZNtLLbFTvSTLAGWpDEFRydzuFEbkMV0CN0LckQCHLSAjqBxj12H+SwL6MTWB+s8E f82Jrfg+EdvDraHhpmVSR5DOHGUITMUM8hG8iSmvZmXv5CC9WbEx5dw+ak9Vfj+bXfrR hGNA== X-Received: by 10.68.191.101 with SMTP id gx5mr106777037pbc.148.1436191975961; Mon, 06 Jul 2015 07:12:55 -0700 (PDT) Received: from localhost.localdomain ([182.225.40.2]) by mx.google.com with ESMTPSA id pr4sm18436546pbb.30.2015.07.06.07.12.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jul 2015 07:12:46 -0700 (PDT) From: Chanho Park X-Google-Original-From: Chanho Park To: kgene@kernel.org, k.kozlowski@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCHv5] ARM: dts: add exynos5422-cpus.dtsi to correct cpu order Date: Mon, 6 Jul 2015 23:12:35 +0900 Message-Id: <1436191955-3650-1-git-send-email-chanho61.park@samsung.com> X-Mailer: git-send-email 2.1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanho Park --- Changes from v4: - Remove temporal patch in e-mail body Changes from v3: - include this exynos5422-cpus.dtsi in the exynos5422-odroidxu3-common.dtsi Changes from v2: - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi - drop compatibles from exynos5422-cpus.dtsi Changes from v1: - rename exynos5422.dtsi to exynos5422-cpus.dtsi - include the dtsi file top of the exynos5422-odroidxu3.dts Secondary cpu booting problem[1] is not resolved yet. Need more investigations to work booting 8 cores correctly. [1]: http://www.spinics.net/lists/linux-samsung-soc/msg45525.html arch/arm/boot/dts/exynos5422-cpus.dtsi | 81 ++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 + 2 files changed, 82 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 0000000..b7f60c8 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,81 @@ +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file to provide cpu ordering + * which could boot a cortex-a7 from cpu0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 8adf455..f603133 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -15,6 +15,7 @@ #include #include #include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" / { memory {