From patchwork Tue Jul 14 00:24:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 6782891 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 08AC9C05AC for ; Tue, 14 Jul 2015 00:24:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13410206CD for ; Tue, 14 Jul 2015 00:24:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2BC5C206DE for ; Tue, 14 Jul 2015 00:24:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751951AbbGNAYt (ORCPT ); Mon, 13 Jul 2015 20:24:49 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:36295 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752049AbbGNAYt (ORCPT ); Mon, 13 Jul 2015 20:24:49 -0400 Received: by pdjr16 with SMTP id r16so71183638pdj.3 for ; Mon, 13 Jul 2015 17:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=XV4zQOBQaiufv7J+fE5UIFlCMdIOxrY0qsT4wf3qakE=; b=MaLoqEXwmZ++p2xjXeq+gS8+CwdHFP8IJgeUgqOH+sly4Jwdq7g0myx8404cUsGeJn cq+APXH4VaXsvGh8IfzkhJApToqLzEh+Q5+NSCoU1M88lClx+ekPMaKfg0HhRxWbITZ6 Eq16ny5z39ENm4PP0y2snJdOh/tbpYeNWumQp9BSHtNrMffzF4hryhOEMJmTLG9P7Rxs v28PqCyHQAUtkS2NdfrKN45Ql/fBmq0LKiVj4eAIQJJpY/vROuE1QwpxyJOGghUBGW33 eE1RnJToX75vcuPpbLYe0cg6jsDYcnUIiXSeLmQCYFxUquBYg/GlaYVl8yRDqyWcpAV/ jvnw== X-Received: by 10.66.118.199 with SMTP id ko7mr72643497pab.147.1436833488622; Mon, 13 Jul 2015 17:24:48 -0700 (PDT) Received: from localhost.localdomain ([112.169.4.226]) by smtp.gmail.com with ESMTPSA id cz1sm19702947pbc.84.2015.07.13.17.24.46 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Jul 2015 17:24:48 -0700 (PDT) From: Chanho Park To: kgene@kernel.org, k.kozlowski@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCHv6] ARM: dts: add exynos5422-cpus.dtsi to correct cpu order Date: Tue, 14 Jul 2015 09:24:01 +0900 Message-Id: <1436833441-8405-1-git-send-email-parkch98@gmail.com> X-Mailer: git-send-email 2.1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The odroid-xu3 board which is based on exynos5422 not exynos5800 is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added exynos5422-cpus.dtsi and reversing cpu orders from exynos5420. Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanho Park --- Change from v4: - Resend patch with correct signed-off Changes from v4: - Remove temporal patch in e-mail body Changes from v3: - include this exynos5422-cpus.dtsi in the exynos5422-odroidxu3-common.dtsi Changes from v2: - drop inclusion of exynos5420.dtsi from exynos5422-cpus.dtsi - drop compatibles from exynos5422-cpus.dtsi Changes from v1: - rename exynos5422.dtsi to exynos5422-cpus.dtsi - include the dtsi file top of the exynos5422-odroidxu3.dts Secondary cpu booting problem[1] is not resolved yet. Need more investigations to work booting 8 cores correctly. [1]: http://www.spinics.net/lists/linux-samsung-soc/msg45525.html arch/arm/boot/dts/exynos5422-cpus.dtsi | 81 ++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 + 2 files changed, 82 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5422-cpus.dtsi diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi new file mode 100644 index 0000000..b7f60c8 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -0,0 +1,81 @@ +/* + * SAMSUNG EXYNOS5422 SoC cpu device tree source + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The + * EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting + * from Cortex-A15 core. + * + * EXYNOS5422 based board files can include this file to provide cpu ordering + * which could boot a cortex-a7 from cpu0. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&cpu0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + cci-control-port = <&cci_control0>; +}; + +&cpu4 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu5 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu6 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x2>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; + +&cpu7 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x3>; + clock-frequency = <1800000000>; + cci-control-port = <&cci_control1>; +}; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 8adf455..f603133 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -15,6 +15,7 @@ #include #include #include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" / { memory {