From patchwork Mon Jul 27 21:28:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Klimov X-Patchwork-Id: 6876801 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BBDDF9F39D for ; Mon, 27 Jul 2015 21:28:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED76A20658 for ; Mon, 27 Jul 2015 21:28:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8184E2071E for ; Mon, 27 Jul 2015 21:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754822AbbG0V2u (ORCPT ); Mon, 27 Jul 2015 17:28:50 -0400 Received: from mail-la0-f49.google.com ([209.85.215.49]:36409 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754525AbbG0V2r (ORCPT ); Mon, 27 Jul 2015 17:28:47 -0400 Received: by lagw2 with SMTP id w2so57068720lag.3 for ; Mon, 27 Jul 2015 14:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:subject:from:to:cc:date:content-type:mime-version :content-transfer-encoding; bh=Moln8c76VT2c2rMgMY/aXhApHgER816pB+giYAOHjgk=; b=L82rBkCEaCo2VG24tEq92orVn/wJE1D12keVx+gHGMbR2Xs8/ggbgyXQ4rxhj/WrK9 OlX8gSPJPnbqm7OKIDt4l0Qb4ZoGmEQG+ID0ag8lfxQCM/rJ3xjLEhSFJZsS86WqGeBA 5+QXYirx+u+SdHXyG11bpEDEhGvV53DIZLIRe5S3YqJ7QEGCSBWomfK4yKwl4QpP/ylf iTq+lM6xzu8HgGOV4ERQgq+wiL2KjOTMhHIT6wNlQMGisB3JJjLr+cbRNQyUTFGt/P0T kT+CmSI9IF0t5pio+/dfA6u/XDDh29Se5KrY/xBrd44PDL7WGfdF7DmAhR60LDDfOVzM N2HA== X-Received: by 10.112.144.199 with SMTP id so7mr29169306lbb.109.1438032526036; Mon, 27 Jul 2015 14:28:46 -0700 (PDT) Received: from [192.168.0.101] (ip-46-73-144-13.bb.netbynet.ru. [46.73.144.13]) by smtp.gmail.com with ESMTPSA id jl4sm4197405lbc.14.2015.07.27.14.28.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jul 2015 14:28:45 -0700 (PDT) Message-ID: <1438032524.17734.48.camel@gmail.com> Subject: [RFC PATCH 2/3] documentation: dt: mct: add desc of optional property use-cp15-phys-counter From: Alexey Klimov To: linux-samsung-soc@vger.kernel.org, daniel.lezcano@linaro.org, dianders@chromium.org, chirantan@chromium.org Cc: klimov.linux@gmail.com, t.dakhran@gmail.com, k.kozlowski@samsung.com, kgene@kernel.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, yury.norov@gmail.com Date: Tue, 28 Jul 2015 00:28:44 +0300 X-Mailer: Evolution 3.16.3-1 Mime-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Alexey Klimov --- .../devicetree/bindings/timer/samsung,exynos4210-mct.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt index 167d5da..c7f6354 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt @@ -36,6 +36,16 @@ Required properties: interrupt might be specified, meaning that all local timers use the same per processor interrupt. +Optional properties: + +- use-cp15-phys-counter : set to advise mct clocksource driver to use ARM + arch timer 64-bit counter as main counter. Access to this coprocessor + counter is faster than access to same counter in mct mmio region. + It was discovered that mct and ARM arch timer are same underlying hardware + on some SoCs. + Only supported for Exynos5-based 32-bit systems which follow the ARMv7 + architecture. + Example 1: In this example, the IP contains two local timers, using separate interrupts, so two local timer interrupts have been specified, in addition to four global timer interrupts.