From patchwork Tue Aug 11 03:46:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 6988071 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8EBA6C05AC for ; Tue, 11 Aug 2015 03:47:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6A4E2054C for ; Tue, 11 Aug 2015 03:47:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D9A820547 for ; Tue, 11 Aug 2015 03:47:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933936AbbHKDrl (ORCPT ); Mon, 10 Aug 2015 23:47:41 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:46408 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933702AbbHKDqb (ORCPT ); Mon, 10 Aug 2015 23:46:31 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NSW00YDEFTGB080@mailout4.samsung.com>; Tue, 11 Aug 2015 12:46:28 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.114]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D4.11.20564.41079C55; Tue, 11 Aug 2015 12:46:28 +0900 (KST) X-AuditID: cbfee690-f796f6d000005054-50-55c970146802 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id C7.6F.23663.41079C55; Tue, 11 Aug 2015 12:46:28 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NSW00KFSFTEM8I0@mmp2.samsung.com>; Tue, 11 Aug 2015 12:46:28 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] clk: samsung: exynos3250: Add MMC2 clock Date: Tue, 11 Aug 2015 12:46:22 +0900 Message-id: <1439264784-30322-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> References: <1439264784-30322-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkSFek4GSowdZbZhbXvzxntZh/5Byr xesXhhb9j18zW2x6fI3V4mPPPVaLy7vmsFnMOL+PyeLiKVeLw2/aWS1+nOlmsVi16w+jA4/H +xut7B6X+3qZPHbOusvusWlVJ5vH5iX1Hn1bVjF6fN4kF8AexWWTkpqTWZZapG+XwJVx/Mh8 toJ/MhXPFn9ibGCcJNHFyMkhIWAicf3eISYIW0ziwr31bF2MXBxCAisYJf7suMEKU7Ru3gN2 iMQsRonpW86xQjhfGCU+bD3IBlLFJqAlsf/FDSCbg0NEIE6ioU8IpIZZ4A2jxJMJ7YwgNcIC thIH+2+zgNgsAqoS03Z8ZQSp5xVwldj0vhZimYLEsuUzwRZzCrhJHL7RCnadEFDJnSO9zCAz JQTOsUvcvfqZHWKOgMS3yYdYQOZICMhKbDrADDFHUuLgihssExiFFzAyrGIUTS1ILihOSi8y 0StOzC0uzUvXS87P3cQIjJPT/55N2MF474D1IUYBDkYlHl4Bz5OhQqyJZcWVuYcYTYE2TGSW Ek3OB0ZjXkm8obGZkYWpiamxkbmlmZI472upn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUa GGN8/9x98djgf6SwsLbA5l/C3qscAnc2vfju1nBs4pPzW6VUt7+bOCH2+8MFLOVc/z2vXH8V lROU3CyzjDdK/JSW0K3OuyVsAawK8+VvfJ9hNqvl2xSJjvj4fJtb/+xYb82SbZkSk7xZ0WHe VyWVXx+WqKok+543DOdni/u8wLv7xWLek0KnJJRYijMSDbWYi4oTAZkbAECOAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jQV2RgpOhBqvfGFhc//Kc1WL+kXOs Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7VAOjTUZqYkpqkUJqXnJ+SmZe uq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7QnUoKZYk5pUChgMTiYiV9O0wTQkPc dC1gGiN0fUOC4HqMDNBAwhrGjONH5rMV/JOpeLb4E2MD4ySJLkZODgkBE4l18x6wQ9hiEhfu rWfrYuTiEBKYxSgxfcs5VgjnC6PEh60H2UCq2AS0JPa/uAFkc3CICMRJNPQJgdQwC7xhlHgy oZ0RpEZYwFbiYP9tFhCbRUBVYtqOr4wg9bwCrhKb3tdCLFOQWLZ8JiuIzSngJnH4RisTiC0E VHLnSC/zBEbeBYwMqxglUguSC4qT0nMN81LL9YoTc4tL89L1kvNzNzGCY/GZ1A7Gg7vcDzEK cDAq8fAKeJ4MFWJNLCuuzD3EKMHBrCTC+8oJKMSbklhZlVqUH19UmpNafIjRFOiuicxSosn5 wDSRVxJvaGxiZmRpZG5oYWRsriTOK7thc6iQQHpiSWp2ampBahFMHxMHp1QD417TgNqr89L1 Ins9hKJPvzdoiTY61/mn/HrezbcakZ+umarXeLf+sOcXyPt7Pd+sLvbTw80Cla921xzMivl/ uP1a5gXdeSf+uBcp5bBo3TadylvIx3zFztWw8dYHjiTl2u7jcff3Hp499xPXGpFtv1nFe6+z v5vmk64fHjxt2h+HHXvuB23fqsRSnJFoqMVcVJwIADO7shXbAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ include/dt-bindings/clock/exynos3250.h | 7 ++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 2105863a3ace..2683cf03e656 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -303,6 +303,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), @@ -389,6 +390,11 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), @@ -539,6 +545,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -634,6 +642,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 89a7d97b002c..fbc9ef61b191 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,7 @@ #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -128,6 +129,8 @@ #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -225,6 +228,7 @@ #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 #define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -252,12 +256,13 @@ #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 #define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 249 +#define CLK_NR_CLKS 250 /* * CMU DMC