| Message ID | 1440414356-1805-4-git-send-email-alim.akhtar@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 24.08.2015 20:05, Alim Akhtar wrote: > This patch correct the nr_clk_ids for fsys0 block s/correct/corrects/ > which is wrongly set to TOP1 clk numbers. > This also adjust the a gate clock order. s/adjust the a/adjusts the/ Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello Krzysztof, On Tue, Aug 25, 2015 at 12:46 PM, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote: > On 24.08.2015 20:05, Alim Akhtar wrote: >> This patch correct the nr_clk_ids for fsys0 block > s/correct/corrects/ > >> which is wrongly set to TOP1 clk numbers. >> This also adjust the a gate clock order. > s/adjust the a/adjusts the/ > will update > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> > Thanks! > Best regards, > Krzysztof > > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index d6c4548..2799568 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -849,13 +849,13 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { }; static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { - GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", - "mout_aclk_fsys0_200_user", - ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 3, 0, 0), GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 4, 0, 0), + GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", + "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS01, 29, 0, 0), @@ -887,7 +887,7 @@ static struct samsung_cmu_info fsys0_cmu_info __initdata = { .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = TOP1_NR_CLK, + .nr_clk_ids = FSYS0_NR_CLK, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), };
This patch correct the nr_clk_ids for fsys0 block which is wrongly set to TOP1 clk numbers. This also adjust the a gate clock order. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> --- drivers/clk/samsung/clk-exynos7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)