From patchwork Tue Sep 1 14:17:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 7105611 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 67E30BEEC1 for ; Tue, 1 Sep 2015 14:17:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5739E204D6 for ; Tue, 1 Sep 2015 14:17:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B5AB20602 for ; Tue, 1 Sep 2015 14:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753364AbbIAORj (ORCPT ); Tue, 1 Sep 2015 10:17:39 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:34930 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752853AbbIAORZ (ORCPT ); Tue, 1 Sep 2015 10:17:25 -0400 Received: by pacdd16 with SMTP id dd16so178482308pac.2 for ; Tue, 01 Sep 2015 07:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=d7r5eKirnSKK/XHZ4tM0KU/2yp/PdhCs8AnJWlANQmw=; b=qavsgLzyA2Yyt/nq4B+a1hHt0HP5thxku4mJIHi/TkZq8nO9lt0zmrVHXYuuRFrGa8 iY7Zbgs1zOikRLe1ZsC5SMc8xs1/LgwXfzAKdeFvMuYYNLVcxrD+zHm0o1wGBelghY+w 22W1bbBbxTHzZ075lvPNMhP3418ygsB93sgsMy9N7L9nYTKossaZXRq/VCJ4BS/bYHMX a9j21QXhurPjLU+hE4OVrKCds3aIzzgpZHGyRiwh4rFNBtjrbggTyoMTqIYNlkGsK+Fk umDn5xYw8r1nQjImfnj7eVXWzYOptWeNidKdDn2dPdZ0tLmXRq8Z+XEa3wQWr9Hv78gG VrPA== X-Received: by 10.67.15.66 with SMTP id fm2mr22278079pad.82.1441117044638; Tue, 01 Sep 2015 07:17:24 -0700 (PDT) Received: from localhost.localdomain ([182.225.40.2]) by smtp.gmail.com with ESMTPSA id lo10sm18458709pab.16.2015.09.01.07.17.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 01 Sep 2015 07:17:23 -0700 (PDT) From: Chanho Park To: kgene@kernel.org, k.kozlowski@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Chanho Park , Kevin Hilman , Javier Martinez Canillas Subject: [PATCHv2] ARM: EXYNOS: reset Little cores when cpu is up Date: Tue, 1 Sep 2015 23:17:03 +0900 Message-Id: <1441117023-25478-1-git-send-email-parkch98@gmail.com> X-Mailer: git-send-email 2.1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The cpu booting of exynos5422 has been still broken since we discussed it in last year[1]. This patch is inspired from Odroid XU3 code (Actually, it was from samsung exynos vendor kernel)[2]. This weird reset code was founded exynos5420 octa cores series SoCs and only required for the first boot core is the Little core (Cortex A7). Some of the exynos5420 boards and all of the exynos5422 boards will require this code. There is two ways to check the little core is the first cpu. One is checking GPG2CON[1] GPIO value and the other is checking the cluster number of the first cpu. I selected the latter because it's more easier than the former. [1]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-June/350632.html [2]:https://patchwork.kernel.org/patch/6782891/ Cc: Kevin Hilman Cc: Javier Martinez Canillas Cc: Krzysztof Kozlowski Tested-by: Kevin Hilman Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Tested-by: Krzysztof Kozlowski --- Changes from v1: .kfc to Little (Cortex A7) and eagle to big (Cortex A15) .append comments about waiting SPARE2 register Changes since RFC: .drop checking soc_is_exynos5800 to extend this codes to exynos5420/5422 boards. .kfc cores will be reset only if the cpu0 is kfc core. .Rebase top of the kukjin's for-next branch arch/arm/mach-exynos/mcpm-exynos.c | 25 ++++++++++++++++++++++++- arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 9bdf547..8926621 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "regs-pmu.h" #include "common.h" @@ -70,7 +71,29 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; - exynos_cpu_power_up(cpunr); + if (!exynos_cpu_power_state(cpunr)) { + exynos_cpu_power_up(cpunr); + + /* This assumes the cluster number of the big cores(Cortex A15) + * is 0 and the Little cores(Cortex A7) is 1. + * When the system was booted from the Little core, + * they should be reset during power up cpu. + */ + if (cluster && + cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) { + /* Before we reset the Little cores, we should wait + * the SPARE2 register is set to 1 because the init + * codes of the iROM will set the register after + * initialization. + */ + while (!pmu_raw_readl(S5P_PMU_SPARE2)) + udelay(10); + + pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu), + EXYNOS_SWRESET); + } + } + return 0; } diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index b761433..fba9068 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -513,6 +513,12 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) #define SPREAD_ENABLE 0xF #define SPREAD_USE_STANDWFI 0xF +#define EXYNOS5420_KFC_CORE_RESET0 BIT(8) +#define EXYNOS5420_KFC_ETM_RESET0 BIT(20) + +#define EXYNOS5420_KFC_CORE_RESET(_nr) \ + ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) + #define EXYNOS5420_BB_CON1 0x0784 #define EXYNOS5420_BB_SEL_EN BIT(31) #define EXYNOS5420_BB_PMOS_EN BIT(7)