From patchwork Fri Sep 4 11:37:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 7121501 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D690C9F380 for ; Fri, 4 Sep 2015 11:52:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0EF0220842 for ; Fri, 4 Sep 2015 11:52:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 164BE20840 for ; Fri, 4 Sep 2015 11:52:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757059AbbIDLwn (ORCPT ); Fri, 4 Sep 2015 07:52:43 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:48671 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757017AbbIDLwl (ORCPT ); Fri, 4 Sep 2015 07:52:41 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU500YYVIBREBB0@mailout1.samsung.com>; Fri, 04 Sep 2015 20:52:39 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.122]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 17.1C.29324.70689E55; Fri, 4 Sep 2015 20:52:39 +0900 (KST) X-AuditID: cbfee68d-f79106d00000728c-6e-55e986073913 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 2D.B2.18629.70689E55; Fri, 4 Sep 2015 20:52:39 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NU500HFUI0Y1N70@mmp2.samsung.com>; Fri, 04 Sep 2015 20:52:39 +0900 (KST) From: Alim Akhtar To: linux-samsung-soc@vger.kernel.org Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, amit.daniel@samsung.com, gautam.vivek@samsung.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Subject: [PATCH 09/11] clk: samsung: exynos7: Corrects CMU_FSYS1 clocks names Date: Fri, 04 Sep 2015 17:07:14 +0530 Message-id: <1441366637-28001-10-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> References: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRmVeSWpSXmKPExsWyRsSkSpe97WWoQdd1fYuGqyEWbVcOslu8 fmFo0f/4NbPFx557rBYzzu9jsrh4ytXi8Jt2VosfZ7pZLFbt+sPowOXx/kYru8flvl4mj52z 7rJ7bFrVyebRt2UVo8fnTXIBbFFcNimpOZllqUX6dglcGa8vvmAsOCxaMX/zIuYGxg1CXYyc HBICJhIPP+1ggbDFJC7cW8/WxcjFISSwglGi6/lydpiijSuuMEEkZjFK7N0ynxUkISTwk1Fi 36oMEJtNQFvi7vQtTCC2iICqxOe2BewgDcwCdxklbn3dCpYQFvCV2D73E9hUFqCiR6u2gtm8 Ah4Su6fuZ4TYpijR/WwCG4jNCRTvunycBWKZu8TPG01g50kIbGOX+PLxGiPEIAGJb5MPARVx ACVkJTYdYIaYIylxcMUNlgmMwgsYGVYxiqYWJBcUJ6UXGeoVJ+YWl+al6yXn525iBMbC6X/P encw3j5gfYhRgINRiYf3xI8XoUKsiWXFlbmHGE2BNkxklhJNzgdGXF5JvKGxmZGFqYmpsZG5 pZmSOK+i1M9gIYH0xJLU7NTUgtSi+KLSnNTiQ4xMHJxSDYyM064Ka2w6qaX1gvWxHDtjapzO Uq/4EqnX/1zCXrN6HVrDuPbHrMJk7tIQ7ilhgqaWt1JmSR4z3lF0uaVfJVTsX9+i+lt1f2oe 9d1jq5lvVZN4eZnRtMLm/yl7d1fOig7dY75yRqP5nb+fQ/dLFPiz5jJe1nE4571/gprkU71C Rr1X2z5MOKrEUpyRaKjFXFScCAD2bJ5cgAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQV32tpehBjtOqFg0XA2xaLtykN3i 9QtDi/7Hr5ktPvbcY7WYcX4fk8XFU64Wh9+0s1r8ONPNYrFq1x9GBy6P9zda2T0u9/Uyeeyc dZfdY9OqTjaPvi2rGD0+b5ILYItqYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQw V1LIS8xNtVVy8QnQdcvMATpMSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhY w5jx+uILxoLDohXzNy9ibmDcINTFyMkhIWAisXHFFSYIW0ziwr31bF2MXBxCArMYJfZumc8K khAS+MkosW9VBojNJqAtcXf6FrAGEQFVic9tC9hBGpgF7jJK3Pq6FSwhLOArsX3uJ3YQmwWo 6NGqrWA2r4CHxO6p+xkhtilKdD+bwAZicwLFuy4fZ4FY5i7x80YT2wRG3gWMDKsYJVILkguK k9JzjfJSy/WKE3OLS/PS9ZLzczcxguPtmfQOxsO73A8xCnAwKvHwnvjxIlSINbGsuDL3EKME B7OSCO/UwJehQrwpiZVVqUX58UWlOanFhxhNgQ6byCwlmpwPTAV5JfGGxibmpsamliYWJmaW SuK8siufhQoJpCeWpGanphakFsH0MXFwSjUw6i+MeVL9vr6fT+u17BSFPVd3XBG/LsK29778 N2tBIffpX+4f+71sVknvh6DinJgek6dd/+5utSlc9uL0qZcbeXg8pTLKTOb94eCYYHix1iKT Qc2E/Ulb7DPrmi2zKpgP+K/Lb9jbcsT80jL9kg2n7s74oMxUlS28Yfkvp7fT4s98n5D09rDc USWW4oxEQy3mouJEALIytvjNAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch rename CMU_FSYS1 clocks names to match with user manual. And also adds missing gate clock for aclk_fsys1_200. Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7.c | 16 ++++++++++------ include/dt-bindings/clock/exynos7-clk.h | 3 ++- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 011685e..f47a2d4 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -517,6 +517,8 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), + GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", + ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), }; static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { @@ -959,9 +961,9 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", /* * List of parent clocks for Muxes in CMU_FSYS1 */ -PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; -PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; -PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; +PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; +PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; +PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; static unsigned long fsys1_clk_regs[] __initdata = { MUX_SEL_FSYS10, @@ -970,11 +972,13 @@ static unsigned long fsys1_clk_regs[] __initdata = { }; static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { - MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, + MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, MUX_SEL_FSYS10, 28, 1), - MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), - MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), + MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, + MUX_SEL_FSYS11, 24, 1), + MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, + MUX_SEL_FSYS11, 28, 1), }; static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 667faed..acdf2e5 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -63,7 +63,8 @@ #define CLK_SCLK_MMC1 7 #define CLK_SCLK_MMC0 8 #define CLK_ACLK_FSYS0_200 9 -#define TOP1_NR_CLK 10 +#define CLK_ACLK_FSYS1_200 10 +#define TOP1_NR_CLK 11 /* CCORE */ #define PCLK_RTC 1