From patchwork Fri Sep 4 11:37:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 7121521 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D1CF5BEEC1 for ; Fri, 4 Sep 2015 11:54:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9CAA920842 for ; Fri, 4 Sep 2015 11:54:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BD0CB20847 for ; Fri, 4 Sep 2015 11:54:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752633AbbIDLyL (ORCPT ); Fri, 4 Sep 2015 07:54:11 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:43778 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752114AbbIDLyJ (ORCPT ); Fri, 4 Sep 2015 07:54:09 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU502KVVIE8I650@mailout4.samsung.com>; Fri, 04 Sep 2015 20:54:08 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.123]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 7E.AB.24422.06689E55; Fri, 4 Sep 2015 20:54:08 +0900 (KST) X-AuditID: cbfee68f-f793b6d000005f66-44-55e98660a67b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 60.4F.23663.06689E55; Fri, 4 Sep 2015 20:54:08 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NU500HFUI0Y1N70@mmp2.samsung.com>; Fri, 04 Sep 2015 20:54:08 +0900 (KST) From: Alim Akhtar To: linux-samsung-soc@vger.kernel.org Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, amit.daniel@samsung.com, gautam.vivek@samsung.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Subject: [PATCH 11/11] clk: samsung: exynos7: Add required clock tree for UFS Date: Fri, 04 Sep 2015 17:07:16 +0530 Message-id: <1441366637-28001-12-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> References: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFLMWRmVeSWpSXmKPExsWyRsSkWjeh7WWowZ9b8hYNV0Ms2q4cZLd4 /cLQov/xa2aLjz33WC1mnN/HZHHxlKvF4TftrBY/znSzWKza9YfRgcvj/Y1Wdo/Lfb1MHjtn 3WX32LSqk82jb8sqRo/Pm+QC2KK4bFJSczLLUov07RK4MlrXXWYuOBRY8XvjY7YGxnuuXYwc HBICJhIvJ9p1MXICmWISF+6tZ+ti5OIQEljBKLHz6lNGiISJxLUt35ggErMYJRZ8/MQKkhAS +MkosXydEojNJqAtcXf6FiYQW0RAVeJz2wJ2kAZmgbuMEre+bmUC2SYs4CtxdaIxSA0LUM2F NT1gC3gFPCS69jQwQSxTlOh+NoENxOYEiV8+zgKxy13i540mNoiabewSjV85IeYISHybfIgF 4hlZiU0HmCFKJCUOrrjBMoFReAEjwypG0dSC5ILipPQiY73ixNzi0rx0veT83E2MwCg4/e9Z /w7GuwesDzEKcDAq8fCe+PEiVIg1say4MvcQoynQhonMUqLJ+cBYyyuJNzQ2M7IwNTE1NjK3 NFMS510o9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA+NuNYGANOutidePKiuLLtvkf75J sT1FrOdiBuedNTr6V+azzT3UtM6vTI73rV5WjmnM1J0TEm8dYMv54fShZ6ed7E6TK9FRMlN9 Arte+hbdZa96k55asHxi8t5Z5Vqn5ye6LPq70fZwllf/LIbJh88pCj0+LjtL7ND5+fmPQnf+ FJ15jW+daokSS3FGoqEWc1FxIgDdW4IyfQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsVy+t9jQd2EtpehBkeeils0XA2xaLtykN3i 9QtDi/7Hr5ktPvbcY7WYcX4fk8XFU64Wh9+0s1r8ONPNYrFq1x9GBy6P9zda2T0u9/Uyeeyc dZfdY9OqTjaPvi2rGD0+b5ILYItqYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQw V1LIS8xNtVVy8QnQdcvMATpMSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhY w5jRuu4yc8GhwIrfGx+zNTDec+1i5OSQEDCRuLblGxOELSZx4d56ti5GLg4hgVmMEgs+fmIF SQgJ/GSUWL5OCcRmE9CWuDt9C1iDiICqxOe2BewgDcwCdxklbn3dCpTg4BAW8JW4OtEYpIYF qObCmh5GEJtXwEOia08D1DJFie5nE9hAbE6Q+OXjLBC73CV+3mhim8DIu4CRYRWjRGpBckFx UnquYV5quV5xYm5xaV66XnJ+7iZGcLQ9k9rBeHCX+yFGAQ5GJR7egm8vQoVYE8uKK3MPMUpw MCuJ8E4NfBkqxJuSWFmVWpQfX1Sak1p8iNEU6LCJzFKiyfnARJBXEm9obGJuamxqaWJhYmap JM4ru/JZqJBAemJJanZqakFqEUwfEwenVAPjHjOjjUlBDkZFFXMr/VJtzzd7vjq+v5XvlCSH d8jxf6pVT69devNg9ap7ZsZVy+/OiBZunnogoHP94UnyR012J3oHc09NXFop2GF512zhYteS y9Vr9qYJhEds1NZ/FyMc9Ovykp7/LXsilc/mzV9wSvyapOqe088ecmtH392psbnUXE9z15oK JZbijERDLeai4kQAlQRqmswCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding required mux/div/gate clocks for UFS controller present on Exynos7. Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7.c | 116 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/exynos7-clk.h | 24 ++++++- 2 files changed, 138 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 43cfee0..ec009be 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -153,6 +153,15 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = { GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", ENABLE_ACLK_TOPC1, 24, 0, 0), + GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 17, 0, 0), + GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 16, 0, 0), + GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 13, 0, 0), + GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 12, 0, 0), + GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", ENABLE_SCLK_TOPC1, 20, 0, 0), GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", @@ -479,12 +488,21 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = { MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), + MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1, + MUX_SEL_TOP1_FSYS0, 0, 2), MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 28, 2), + MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1, + MUX_SEL_TOP1_FSYS1, 0, 2), + MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1, + MUX_SEL_TOP1_FSYS1, 16, 2), + MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), + MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1, + MUX_SEL_TOP1_FSYS11, 24, 2), }; static struct samsung_div_clock top1_div_clks[] __initdata = { @@ -493,6 +511,13 @@ static struct samsung_div_clock top1_div_clks[] __initdata = { DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", DIV_TOP13, 28, 4), + DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1", + "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6), + + DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20", + "mout_sclk_ufsunipro20", + DIV_TOP1_FSYS1, 16, 6), + DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", DIV_TOP1_FSYS0, 16, 10), DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", @@ -502,6 +527,9 @@ static struct samsung_div_clock top1_div_clks[] __initdata = { DIV_TOP1_FSYS11, 0, 10), DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", DIV_TOP1_FSYS11, 12, 10), + + DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m", + "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), }; static struct samsung_gate_clock top1_gate_clks[] __initdata = { @@ -510,6 +538,12 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), + GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1", + ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20", + ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", @@ -519,6 +553,10 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", + "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, + 24, CLK_SET_RATE_PARENT, 0), }; static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { @@ -958,22 +996,54 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ #define MUX_SEL_FSYS10 0x0200 #define MUX_SEL_FSYS11 0x0204 +#define MUX_SEL_FSYS12 0x0208 +#define DIV_FSYS1 0x0600 #define ENABLE_ACLK_FSYS1 0x0800 +#define ENABLE_PCLK_FSYS1 0x0900 +#define ENABLE_SCLK_FSYS11 0x0A04 +#define ENABLE_SCLK_FSYS12 0x0A08 +#define ENABLE_SCLK_FSYS13 0x0A0C /* * List of parent clocks for Muxes in CMU_FSYS1 */ PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; +PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m", + "sclk_phy_fsys1_26m" }; PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; +PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" }; +PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" }; +PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" }; +PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; + +/* fixed rate clocks used in the FSYS1 block */ +struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { + FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, + CLK_IS_ROOT, 300000000), + FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, + CLK_IS_ROOT, 300000000), + FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, + CLK_IS_ROOT, 300000000), +}; static unsigned long fsys1_clk_regs[] __initdata = { MUX_SEL_FSYS10, MUX_SEL_FSYS11, + MUX_SEL_FSYS12, + DIV_FSYS1, ENABLE_ACLK_FSYS1, + ENABLE_PCLK_FSYS1, + ENABLE_SCLK_FSYS11, + ENABLE_SCLK_FSYS12, + ENABLE_SCLK_FSYS13, }; static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { + MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", + mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), + MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, + MUX_SEL_FSYS10, 20, 2), MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, MUX_SEL_FSYS10, 28, 1), @@ -981,18 +1051,64 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { MUX_SEL_FSYS11, 24, 1), MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, MUX_SEL_FSYS11, 28, 1), + MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p, + MUX_SEL_FSYS11, 20, 1), + + MUX(0, "mout_phyclk_ufs20_rx1_symbol_user", + mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1), + MUX(0, "mout_phyclk_ufs20_rx0_symbol_user", + mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1), + MUX(0, "mout_phyclk_ufs20_tx0_symbol_user", + mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), +}; + +static struct samsung_div_clock fsys1_div_clks[] __initdata = { + DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", + DIV_FSYS1, 0, 2), }; static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { + GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", + "mout_sclk_ufsunipro20_user", + ENABLE_SCLK_FSYS11, 20, 0, 0), + GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", ENABLE_ACLK_FSYS1, 29, 0, 0), GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", ENABLE_ACLK_FSYS1, 30, 0, 0), + + GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1", + ENABLE_ACLK_FSYS1, 31, 0, 0), + GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user", + ENABLE_PCLK_FSYS1, 30, 0, 0), + + GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user", + "mout_phyclk_ufs20_rx1_symbol_user", + ENABLE_SCLK_FSYS12, 16, 0, 0), + GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user", + "mout_phyclk_ufs20_rx0_symbol_user", + ENABLE_SCLK_FSYS12, 24, 0, 0), + GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user", + "mout_phyclk_ufs20_tx0_symbol_user", + ENABLE_SCLK_FSYS12, 28, 0, 0), + + GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY, + "oscclk_phy_clkout_embedded_combo_phy", + "fin_pll", + ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0), + + GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m", + "mout_fsys1_phyclk_sel1", + ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), }; static struct samsung_cmu_info fsys1_cmu_info __initdata = { + .fixed_clks = fixed_rate_clks_fsys1, + .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), .mux_clks = fsys1_mux_clks, .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), + .div_clks = fsys1_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), .gate_clks = fsys1_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), .nr_clk_ids = FSYS1_NR_CLK, diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index acdf2e5..10c5586 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -64,7 +64,14 @@ #define CLK_SCLK_MMC0 8 #define CLK_ACLK_FSYS0_200 9 #define CLK_ACLK_FSYS1_200 10 -#define TOP1_NR_CLK 11 +#define CLK_SCLK_PHY_FSYS1 11 +#define CLK_SCLK_PHY_FSYS1_26M 12 +#define MOUT_SCLK_UFSUNIPRO20 13 +#define DOUT_SCLK_UFSUNIPRO20 14 +#define CLK_SCLK_UFSUNIPRO20 15 +#define DOUT_SCLK_PHY_FSYS1 16 +#define DOUT_SCLK_PHY_FSYS1_26M 17 +#define TOP1_NR_CLK 18 /* CCORE */ #define PCLK_RTC 1 @@ -139,7 +146,20 @@ /* FSYS1 */ #define ACLK_MMC1 1 #define ACLK_MMC0 2 -#define FSYS1_NR_CLK 3 +#define PHYCLK_UFS20_TX0_SYMBOL 3 +#define PHYCLK_UFS20_RX0_SYMBOL 4 +#define PHYCLK_UFS20_RX1_SYMBOL 5 +#define ACLK_UFS20_LINK 6 +#define SCLK_UFSUNIPRO20_USER 7 +#define PHYCLK_UFS20_RX1_SYMBOL_USER 8 +#define PHYCLK_UFS20_RX0_SYMBOL_USER 9 +#define PHYCLK_UFS20_TX0_SYMBOL_USER 10 +#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11 +#define SCLK_COMBO_PHY_EMBEDDED_26M 12 +#define DOUT_PCLK_FSYS1 13 +#define PCLK_GPIO_FSYS1 14 +#define MOUT_FSYS1_PHYCLK_SEL1 15 +#define FSYS1_NR_CLK 16 /* MSCL */ #define USERMUX_ACLK_MSCL_532 1