From patchwork Fri Sep 4 11:37:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 7121411 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C3D0FBEEC1 for ; Fri, 4 Sep 2015 11:48:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D76D32083C for ; Fri, 4 Sep 2015 11:48:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C5AA20789 for ; Fri, 4 Sep 2015 11:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753032AbbIDLsF (ORCPT ); Fri, 4 Sep 2015 07:48:05 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:42620 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751255AbbIDLsD (ORCPT ); Fri, 4 Sep 2015 07:48:03 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU5006FYI41WL00@mailout4.samsung.com>; Fri, 04 Sep 2015 20:48:01 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.123]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id A0.72.17770.1F489E55; Fri, 4 Sep 2015 20:48:01 +0900 (KST) X-AuditID: cbfee691-f79ca6d00000456a-a0-55e984f1e73c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id D1.32.18629.1F489E55; Fri, 4 Sep 2015 20:48:01 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NU500HFUI0Y1N70@mmp2.samsung.com>; Fri, 04 Sep 2015 20:48:01 +0900 (KST) From: Alim Akhtar To: linux-samsung-soc@vger.kernel.org Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, amit.daniel@samsung.com, gautam.vivek@samsung.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Subject: [PATCH 01/11] clk: samsung: exynos7: Change the CMU_TOPC block clock name Date: Fri, 04 Sep 2015 17:07:06 +0530 Message-id: <1441366637-28001-2-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> References: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDLMWRmVeSWpSXmKPExsWyRsSkWvdjy8tQg+bT2hYNV0Ms2q4cZLd4 /cLQov/xa2aLjz33WC1mnN/HZHHxlKvF4TftrBY/znSzWKza9YfRgcvj/Y1Wdo/Lfb1MHjtn 3WX32LSqk82jb8sqRo/Pm+QC2KK4bFJSczLLUov07RK4Mg7s/MhacMeuYt9L3wbGM2ZdjJwc EgImEgtmL2aFsMUkLtxbz9bFyMUhJLCCUWL9nd/MMEUzHm9ihkjMYpR4cvU0VNVPRolfZxoY QarYBLQl7k7fwgRiiwioSnxuW8AOUsQscJdR4tbXrUAJDg5hgRCJR2d5QWpYgGp2XNsPVs8r 4C4x7fROdohtihLdzyawgdicAh4SXZePs4DYQkA1P280gS2WENjFLvF89WkmiEECEt8mH2IB mS8hICux6QDU1ZISB1fcYJnAKLyAkWEVo2hqQXJBcVJ6kalecWJucWleul5yfu4mRmAknP73 bOIOxvsHrA8xCnAwKvHwSnx5ESrEmlhWXJl7iNEUaMNEZinR5HxgvOWVxBsamxlZmJqYGhuZ W5opifPqSP8MFhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cC4v/l40rmjRnOFXE8WXhLZcrP3 oY3ARv2Hke+OdquWXI44evz/tbggtyM3JyhN++Ox77fnJecbsQeWZE81qd6S+1Xq6gSfcrX3 f7RbWR6sOVQVeSJgn5qS34lDdc/+8OrUWqg2c/2J1dR77vbsvqTBlmuGYQtc72u+/KWYJrLK QWYKo9RZ/zopJZbijERDLeai4kQAtvlt5H8CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsVy+t9jQd2PLS9DDW7tVLZouBpi0XblILvF 6xeGFv2PXzNbfOy5x2ox4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDlwe72+0sntc7utl8tg5 6y67x6ZVnWwefVtWMXp83iQXwBbVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlh rqSQl5ibaqvk4hOg65aZA3SYkkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCw hjHjwM6PrAV37Cr2vfRtYDxj1sXIySEhYCIx4/EmZghbTOLCvfVsXYxcHEICsxglnlw9DeX8 ZJT4daaBEaSKTUBb4u70LUwgtoiAqsTntgXsIEXMAncZJW593QqU4OAQFgiReHSWF6SGBahm x7X9YPW8Au4S007vZIfYpijR/WwCG4jNKeAh0XX5OAuILQRU8/NGE9sERt4FjAyrGCVSC5IL ipPSc43yUsv1ihNzi0vz0vWS83M3MYKj7Zn0DsbDu9wPMQpwMCrx8J748SJUiDWxrLgy9xCj BAezkgjv1MCXoUK8KYmVValF+fFFpTmpxYcYTYEOm8gsJZqcD0wEeSXxhsYm5qbGppYmFiZm lkrivLIrn4UKCaQnlqRmp6YWpBbB9DFxcEo1MO5ze1VklTGrIerLj7Onbwr/33b15bGr58yy tyc/SmTj+aP++uOv03scjh/x83bs+8uyszeeNWZx6aFbCieWZ0z9Hn421z5kymablPXpc26m FO0Mjn1V2838O1BR6JHZAw7/v7stO8LjV4lz2G5rnHDZ7bRkNitDn6rFZSn1Eyfz6+MKxQVv PFRiKc5INNRiLipOBADBh9PFzAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Corrects the CMU_TOPC block clock name as per user manual. This also adds few of the missing gate clocks of topc block. This does not change any functionalies. Signed-off-by: Alim Akhtar --- drivers/clk/samsung/clk-exynos7.c | 90 +++++++++++++++++++------------ include/dt-bindings/clock/exynos7-clk.h | 11 +++- 2 files changed, 67 insertions(+), 34 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 380608b..2394bde 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -35,38 +35,39 @@ #define DIV_TOPC1 0x0604 #define DIV_TOPC3 0x060C #define ENABLE_ACLK_TOPC1 0x0804 +#define ENABLE_SCLK_TOPC1 0x0A04 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { - FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), + FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), FFACTOR(0, "ffac_topc_bus0_pll_div4", "ffac_topc_bus0_pll_div2", 1, 2, 0), - FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), - FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), - FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), + FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), + FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), + FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), }; /* List of parent clocks for Muxes in CMU_TOPC */ -PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; -PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; -PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; -PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; -PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; +PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; +PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; +PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; +PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; +PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; -PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", - "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", - "mout_sclk_mfc_pll_cmuc" }; +PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", + "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", + "mout_topc_mfc_pll_half" }; -PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", +PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; -PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", +PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", "ffac_topc_bus1_pll_div2"}; -PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", +PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", "ffac_topc_cc_pll_div2"}; -PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", +PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", "ffac_topc_mfc_pll_div2"}; -PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", +PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", "ffac_topc_bus0_pll_div2"}; static unsigned long topc_clk_regs[] __initdata = { @@ -90,22 +91,26 @@ static unsigned long topc_clk_regs[] __initdata = { }; static struct samsung_mux_clock topc_mux_clks[] __initdata = { - MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), - MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), - MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), - MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), - - MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, + MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, + MUX_SEL_TOPC0, 0, 1), + MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, + MUX_SEL_TOPC0, 4, 1), + MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, + MUX_SEL_TOPC0, 8, 1), + MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, + MUX_SEL_TOPC0, 12, 1), + MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, MUX_SEL_TOPC0, 16, 2), - MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, + MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, MUX_SEL_TOPC0, 20, 1), - MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, + MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, MUX_SEL_TOPC0, 24, 1), - MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, + MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, MUX_SEL_TOPC0, 28, 1), - MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), - MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, + MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, + MUX_SEL_TOPC1, 0, 1), + MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1), MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), @@ -123,15 +128,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = { DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", DIV_TOPC1, 24, 4), - DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", + DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", DIV_TOPC3, 0, 4), - DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", + DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", DIV_TOPC3, 8, 4), - DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", + DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", DIV_TOPC3, 12, 4), - DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", + DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", DIV_TOPC3, 16, 4), - DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", + DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", DIV_TOPC3, 28, 4), }; @@ -143,6 +148,25 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { static struct samsung_gate_clock topc_gate_clks[] __initdata = { GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", ENABLE_ACLK_TOPC1, 20, 0, 0), + + GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", + ENABLE_SCLK_TOPC1, 20, 0, 0), + GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 17, 0, 0), + GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 16, 0, 0), + GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 13, 0, 0), + GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 12, 0, 0), + GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", + ENABLE_SCLK_TOPC1, 5, 0, 0), + GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", + ENABLE_SCLK_TOPC1, 4, 0, 0), + GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", + ENABLE_SCLK_TOPC1, 1, 0, 0), + GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", + ENABLE_SCLK_TOPC1, 0, 0, 0), }; static struct samsung_pll_clock topc_pll_clks[] __initdata = { diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index e33c75a..b63eba6 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -21,7 +21,16 @@ #define ACLK_MSCL_532 8 #define DOUT_SCLK_AUD_PLL 9 #define FOUT_AUD_PLL 10 -#define TOPC_NR_CLK 11 +#define SCLK_AUD_PLL 11 +#define SCLK_MFC_PLL_B 12 +#define SCLK_MFC_PLL_A 13 +#define SCLK_BUS1_PLL_B 14 +#define SCLK_BUS1_PLL_A 15 +#define SCLK_BUS0_PLL_B 16 +#define SCLK_BUS0_PLL_A 17 +#define SCLK_CC_PLL_B 18 +#define SCLK_CC_PLL_A 19 +#define TOPC_NR_CLK 20 /* TOP0 */ #define DOUT_ACLK_PERIC1 1