From patchwork Fri Sep 4 11:37:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 7121491 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 344D29F380 for ; Fri, 4 Sep 2015 11:52:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4DA4A20841 for ; Fri, 4 Sep 2015 11:52:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 586AE20840 for ; Fri, 4 Sep 2015 11:52:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755621AbbIDLwF (ORCPT ); Fri, 4 Sep 2015 07:52:05 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:45347 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751034AbbIDLwD (ORCPT ); Fri, 4 Sep 2015 07:52:03 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU5006KXIAQWL00@mailout4.samsung.com>; Fri, 04 Sep 2015 20:52:02 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.123]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 8D.0E.28411.2E589E55; Fri, 4 Sep 2015 20:52:02 +0900 (KST) X-AuditID: cbfee68e-f79c56d000006efb-11-55e985e2a1d3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id A7.A2.18629.2E589E55; Fri, 4 Sep 2015 20:52:02 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NU500HFUI0Y1N70@mmp2.samsung.com>; Fri, 04 Sep 2015 20:52:02 +0900 (KST) From: Alim Akhtar To: linux-samsung-soc@vger.kernel.org Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, amit.daniel@samsung.com, gautam.vivek@samsung.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Subject: [PATCH 08/11] clk: samsung: exynos7: Corrects CMU_FSYS0 clocks names Date: Fri, 04 Sep 2015 17:07:13 +0530 Message-id: <1441366637-28001-9-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> References: <1441366637-28001-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRmVeSWpSXmKPExsWyRsSkWvdR68tQg+lLpSwaroZYtF05yG7x +oWhRf/j18wWH3vusVrMOL+PyeLiKVeLw2/aWS1+nOlmsVi16w+jA5fH+xut7B6X+3qZPHbO usvusWlVJ5tH35ZVjB6fN8kFsEVx2aSk5mSWpRbp2yVwZfR8+c9c8Fmq4sys/0wNjFPFuxg5 OSQETCRuTlzNCGGLSVy4t56ti5GLQ0hgBaPE4ef7mGCKej4tZYdIzGKUOL/yHyuE85NRYvfx 28wgVWwC2hJ3p28B6xARUJX43LYArINZ4C6jxK2vW8ESwgK+En2djawgNgtQ0fcVu4HiHBy8 Au4SK74xQ2xTlOh+NoENxOYU8JDounycBcQWAir5eaMJ7DwJgV3sEkt2fYeaIyDxbfIhFpA5 EgKyEpsOQM2RlDi44gbLBEbhBYwMqxhFUwuSC4qT0ouM9IoTc4tL89L1kvNzNzECY+H0v2d9 OxhvHrA+xCjAwajEw3vix4tQIdbEsuLK3EOMpkAbJjJLiSbnAyMuryTe0NjMyMLUxNTYyNzS TEmcN0HqZ7CQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxsXdzT8OGfzLKBC3ncN5Wf/Y5xw/ xTNzz/B3f7IKSfS/sHzvu76CyilHy/vC99x65nPaprZEdV2cyb3nGlsVQ56/zt98/nUtA/uM Vt7ZHP6zEg7uv8756I6o00Qm+59XNItnvdC9uUCDIVNHIO3+0SU/dDhfBJucupfWmbNsYpPt 6dXH842TPiqxFGckGmoxFxUnAgAkYfUcgAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQd1HrS9DDWZ+F7JouBpi0XblILvF 6xeGFv2PXzNbfOy5x2ox4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDlwe72+0sntc7utl8tg5 6y67x6ZVnWwefVtWMXp83iQXwBbVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlh rqSQl5ibaqvk4hOg65aZA3SYkkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCw hjGj58t/5oLPUhVnZv1namCcKt7FyMkhIWAi0fNpKTuELSZx4d56ti5GLg4hgVmMEudX/mOF cH4ySuw+fpsZpIpNQFvi7vQtTCC2iICqxOe2BewgRcwCdxklbn3dCpYQFvCV6OtsZAWxWYCK vq/YDRTn4OAVcJdY8Y0ZYpuiRPezCWwgNqeAh0TX5eMsILYQUMnPG01sExh5FzAyrGKUSC1I LihOSs81ykst1ytOzC0uzUvXS87P3cQIjrdn0jsYD+9yP8QowMGoxMN74seLUCHWxLLiytxD jBIczEoivFMDX4YK8aYkVlalFuXHF5XmpBYfYjQFumsis5Rocj4wFeSVxBsam5ibGptamliY mFkqifPKrnwWKiSQnliSmp2aWpBaBNPHxMEp1cA4RWJavHJb7J7F+venXVtw+KrnlZSPYXf4 7irbPvUJna/20bxMgY3baeK619JWq1i/N/etC7JTm6KgVfpp+8/Kt+yT3z5p/vdn2e5J8+yv +n8t7nylWP/V6Y+7Hqv15t3XJtuLzdh9XVZLMEGKJ3/axIq9/m2PNx0ssuS6xXZG4NDrCjXH QN7nSizFGYmGWsxFxYkANrCKK80CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch rename CMU_FSYS0 clocks names to match with user manual. And also adds missing gate clock for aclk_fsys0_200. Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7.c | 24 ++++++++++++++---------- include/dt-bindings/clock/exynos7-clk.h | 3 ++- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 75db751..011685e 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -514,6 +514,9 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = { ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", + ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), }; static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { @@ -851,13 +854,13 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", /* * List of parent clocks for Muxes in CMU_FSYS0 */ -PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; -PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; +PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; +PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; -PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; -PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", +PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; +PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_phyclock" }; -PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", +PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_pipe_pclk" }; /* fixed rate clocks used in the FSYS0 block */ @@ -880,18 +883,19 @@ static unsigned long fsys0_clk_regs[] __initdata = { }; static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { - MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, + MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, MUX_SEL_FSYS00, 24, 1), - MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), - MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, + MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, + MUX_SEL_FSYS01, 24, 1), + MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, MUX_SEL_FSYS01, 28, 1), MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", - mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, + mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, MUX_SEL_FSYS02, 24, 1), MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", - mout_phyclk_usbdrd300_udrd30_phyclk_p, + mout_phyclk_usbdrd300_udrd30_phyclk_user_p, MUX_SEL_FSYS02, 28, 1), }; diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 2876654..667faed 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -62,7 +62,8 @@ #define CLK_SCLK_MMC2 6 #define CLK_SCLK_MMC1 7 #define CLK_SCLK_MMC0 8 -#define TOP1_NR_CLK 9 +#define CLK_ACLK_FSYS0_200 9 +#define TOP1_NR_CLK 10 /* CCORE */ #define PCLK_RTC 1