From patchwork Thu Sep 10 08:44:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 7152821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E2D56BEEC1 for ; Thu, 10 Sep 2015 08:59:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0541A20874 for ; Thu, 10 Sep 2015 08:59:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11F1F20871 for ; Thu, 10 Sep 2015 08:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751446AbbIJI72 (ORCPT ); Thu, 10 Sep 2015 04:59:28 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:48877 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751294AbbIJI70 (ORCPT ); Thu, 10 Sep 2015 04:59:26 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NUG00R1VEB0BT00@mailout4.samsung.com>; Thu, 10 Sep 2015 17:59:24 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id AE.C0.28411.C6641F55; Thu, 10 Sep 2015 17:59:24 +0900 (KST) X-AuditID: cbfee68e-f79c56d000006efb-f1-55f1466c8b97 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 58.8C.23663.C6641F55; Thu, 10 Sep 2015 17:59:24 +0900 (KST) Received: from exypnos.sisodomain.com ([107.108.73.28]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NUG00HE8E111EG1@mmp2.samsung.com>; Thu, 10 Sep 2015 17:59:24 +0900 (KST) From: Alim Akhtar To: linux-samsung-soc@vger.kernel.org Cc: s.nawrocki@samsung.com, tomasz.figa@gmail.com, kgene@kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, amit.daniel@samsung.com, gautam.vivek@samsung.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org Subject: [PATCH v2 07/12] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names Date: Thu, 10 Sep 2015 14:14:32 +0530 Message-id: <1441874677-24148-8-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1441874677-24148-1-git-send-email-alim.akhtar@samsung.com> References: <1441874677-24148-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDLMWRmVeSWpSXmKPExsWyRsSkVjfH7WOoQfM3I4uGqyEWbVcOslu8 fmFo0f/4NbPFx557rBYzzu9jsrh4ytXi8Jt2VosfZ7pZLFbt+sPowOXx/kYru8flvl4mj52z 7rJ7bFrVyebRt2UVo8fnTXIBbFFcNimpOZllqUX6dglcGVN6V7IU7FCuePZ2B2sD4125LkZO DgkBE4mLTztYIWwxiQv31rOB2EICKxgl1k5kgqm5tmQaSxcjF1B8FqPEksNfGSGcn4wS209N ZwepYhPQlrg7fQtYh4iAqsTntgXsIEXMAncZJW593QqWEBYIlvj6czWYzQJU9LrpOtA6Dg5e AXeJN0vcILYpSnQ/mwB2BaeAh8S0h3NYIS5yl1h2fgUryEwJgW3sEg/XbGWDmCMg8W3yIRaQ ORICshKbDjBDzJGUOLjiBssERuEFjAyrGEVTC5ILipPSi4z0ihNzi0vz0vWS83M3MQIj4fS/ Z307GG8esD7EKMDBqMTDm3DxQ6gQa2JZcWXuIUZToA0TmaVEk/OB8ZZXEm9obGZkYWpiamxk bmmmJM6bIPUzWEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVAOj7sKrjypv7OT8XLIzY/2SA0Jy B/MM1tcLTDBTlvrTfH3hlK31yhv+5/U0KqY4hp8r2XdZddKEskL23sDSM/8zPZWUNr3W3Pc/ Zav0bem7Ms8LdsvqWPczhh5QV433vv2P5fJjq2ui6+dLSfQUTpLgdePcWe477Xjw3Tm8DHzf H0dazAuNabZQYinOSDTUYi4qTgQA89Rn3n8CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFIsWRmVeSWpSXmKPExsVy+t9jQd0ct4+hBtsWals0XA2xaLtykN3i 9QtDi/7Hr5ktPvbcY7WYcX4fk8XFU64Wh9+0s1r8ONPNYrFq1x9GBy6P9zda2T0u9/Uyeeyc dZfdY9OqTjaPvi2rGD0+b5ILYItqYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQw V1LIS8xNtVVy8QnQdcvMATpMSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhY w5gxpXclS8EO5Ypnb3ewNjDeleti5OSQEDCRuLZkGguELSZx4d56ti5GLg4hgVmMEksOf2WE cH4ySmw/NZ0dpIpNQFvi7vQtTCC2iICqxOe2BewgRcwCdxklbn3dCpYQFgiW+PpzNZjNAlT0 uuk60FgODl4Bd4k3S9wgtilKdD+bwAZicwp4SEx7OIcVxBYCKll2fgXrBEbeBYwMqxglUguS C4qT0nMN81LL9YoTc4tL89L1kvNzNzGC4+2Z1A7Gg7vcDzEKcDAq8fAmXPwQKsSaWFZcmXuI UYKDWUmEN207UIg3JbGyKrUoP76oNCe1+BCjKdBdE5mlRJPzgakgryTe0NjE3NTY1NLEwsTM UkmcV3bls1AhgfTEktTs1NSC1CKYPiYOTqkGxu5tiTsXTuybti4tXXB1xKSOL0XewncMv+fP 4CqfVDqz/3HPhaXS5juKZ1XP0chIeaDcO+1TTXHXGRO54NUzpj22fKre/eDHZw+3Q/7zfM2P veReIhA9TTzjrEjmtsTK73yqYR/vW/FqVfwOk5T+Ede0zqj4kPqFNX2yxqLS568/+nL+kszv PCWW4oxEQy3mouJEAG4ZiHTNAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch renames CMU_PERIC1 clocks names to match with user manual. And also adds missing gate clock for aclk_peric1_66. Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos7.c | 38 ++++++++++++++++--------------- include/dt-bindings/clock/exynos7-clk.h | 3 ++- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index b819fdd..7796712 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -343,6 +343,8 @@ static struct samsung_div_clock top0_div_clks[] __initdata = { static struct samsung_gate_clock top0_gate_clks[] __initdata = { GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), + GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", + ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), @@ -665,15 +667,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", exynos7_clk_peric0_init); /* List of parent clocks for Muxes in CMU_PERIC1 */ -PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; -PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; -PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; -PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; -PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; -PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; -PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; -PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; -PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; +PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; +PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; +PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; +PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; +PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; +PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; +PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; +PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; +PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; static unsigned long peric1_clk_regs[] __initdata = { MUX_SEL_PERIC10, @@ -684,24 +686,24 @@ static unsigned long peric1_clk_regs[] __initdata = { }; static struct samsung_mux_clock peric1_mux_clks[] __initdata = { - MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, + MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, MUX_SEL_PERIC10, 0, 1), - MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, + MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, + MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, + MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, + MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, + MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), - MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, + MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, MUX_SEL_PERIC11, 20, 1), - MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, + MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, MUX_SEL_PERIC11, 24, 1), - MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, + MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, MUX_SEL_PERIC11, 28, 1), }; diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 256188a..2876654 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -50,7 +50,8 @@ #define CLK_SCLK_PCM1 13 #define CLK_SCLK_I2S1 14 #define CLK_ACLK_PERIC0_66 15 -#define TOP0_NR_CLK 16 +#define CLK_ACLK_PERIC1_66 16 +#define TOP0_NR_CLK 17 /* TOP1 */ #define DOUT_ACLK_FSYS1_200 1