From patchwork Wed Oct 14 10:44:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 7391911 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4AD6B9F1B9 for ; Wed, 14 Oct 2015 10:44:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 53059207B0 for ; Wed, 14 Oct 2015 10:44:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6A1242073B for ; Wed, 14 Oct 2015 10:44:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753094AbbJNKos (ORCPT ); Wed, 14 Oct 2015 06:44:48 -0400 Received: from mail-wi0-f175.google.com ([209.85.212.175]:34193 "EHLO mail-wi0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753145AbbJNKol (ORCPT ); Wed, 14 Oct 2015 06:44:41 -0400 Received: by wicgb1 with SMTP id gb1so124349350wic.1; Wed, 14 Oct 2015 03:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=h/pd9qr2V3BDf+UqN6mwWATkvrRJPYAirOwMuafHdRk=; b=E//RNZY3fg9dFpUJfaa2Ja19QZPLf2dNLbxQUBWv4E74IPhJ6vm3VN4B3Fgbq5QTmO Abu/G8eX14Oo+XPCPz1RgCEYpCRVMC1PUzO0H9JUEHmYr8QG87KVs68lFGwl/CRcUJJj NQ+LwpsC3rDwVP6LASk6uaWWNBN35DvCmDOMAFfxxKmuXfUaYPWJ9LWt6kvwXBdUXxO+ y6G34Nuxh/zsXB0AQcOwtCrOEKq7zQGgBQsdyJwnk+tad+zZb1s+MBxkCIVSmxo5ZWg1 Fw+8kmk7wcFQazaKt1TibjUcuRm5TtPCzaVs1wtt6atdVXqQqd+jO64yqMd/VeBUJ1gH 3sfw== X-Received: by 10.194.84.42 with SMTP id v10mr3571493wjy.1.1444819480167; Wed, 14 Oct 2015 03:44:40 -0700 (PDT) Received: from cizrna.lan ([109.72.12.150]) by smtp.gmail.com with ESMTPSA id ht5sm6592063wib.10.2015.10.14.03.44.38 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Oct 2015 03:44:39 -0700 (PDT) From: Tomeu Vizoso To: linux-kernel@vger.kernel.org Cc: Gustavo Padovan , Javier Martinez Canillas , Seung-Woo Kim , Kukjin Kim , Inki Dae , Kyungmin Park , Krzysztof Kozlowski , Joonyoung Shim , Tomeu Vizoso , Russell King , devicetree@vger.kernel.org, Kumar Gala , Ian Campbell , linux-samsung-soc@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain Date: Wed, 14 Oct 2015 12:44:17 +0200 Message-Id: <1444819457-27519-3-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1444819457-27519-1-git-send-email-tomeu.vizoso@collabora.com> References: <1444819457-27519-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds to the node of the DISP1 power domain the two clocks that need to be reparented while the domain is powered off: CLK_MOUT_ACLK200_DISP1_SUB and CLK_MOUT_ACLK300_DISP1_SUB. Otherwise the state is unknown at power up and the mixer's clocks are all messed up. Signed-off-by: Tomeu Vizoso Link: http://lkml.kernel.org/g/561CDC33.7050103@collabora.com Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b24610ea8c2a..88b9cf5f226f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -130,6 +130,10 @@ compatible = "samsung,exynos4210-pd"; reg = <0x100440A0 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_ACLK200_DISP1_SUB>, + <&clock CLK_MOUT_ACLK300_DISP1_SUB>; + clock-names = "oscclk", "clk0", "clk1"; }; clock: clock-controller@10010000 {