From patchwork Tue Oct 20 09:15:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 7444781 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4EC739F1B9 for ; Tue, 20 Oct 2015 09:22:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02D2620846 for ; Tue, 20 Oct 2015 09:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B824F2041F for ; Tue, 20 Oct 2015 09:22:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752706AbbJTJWK (ORCPT ); Tue, 20 Oct 2015 05:22:10 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:50839 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750785AbbJTJWF (ORCPT ); Tue, 20 Oct 2015 05:22:05 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NWI01NBCI0S5KA0@mailout1.samsung.com>; Tue, 20 Oct 2015 18:22:04 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.122]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 42.5C.05284.BB706265; Tue, 20 Oct 2015 18:22:04 +0900 (KST) X-AuditID: cbfee68f-f796f6d0000014a4-41-562607bb4910 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 38.39.18629.BB706265; Tue, 20 Oct 2015 18:22:03 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NWI005AZHSYDV10@mmp2.samsung.com>; Tue, 20 Oct 2015 18:22:03 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, p.fedin@samsung.com, thomas.ab@samsung.com, andi.shyti@samsung.com, Pankaj Dubey Subject: [PATCH v5 8/8] ARM: EXYNOS: Remove SROM related register settings from mach-exynos Date: Tue, 20 Oct 2015 14:45:39 +0530 Message-id: <1445332540-12814-9-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.4.5 In-reply-to: <1445332540-12814-1-git-send-email-pankaj.dubey@samsung.com> References: <1445332540-12814-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsWyRsSkSncPu1qYwSU9i+1HnrFavH5haNG7 4CqbxabH11gtLu+aw2Yx4/w+JotXl1axWSza+oXdomMZowOnx+Yl9R59W1YxenzeJBfAHMVl k5Kak1mWWqRvl8CVsaHrOHvBLYuKrpNXmRoYV+p3MXJwSAiYSNzqNeli5AQyxSQu3FvP1sXI xSEksIJR4uPniYwQCROJvbe+sEAkZjFKLDi7iRHCaWWSmHdjEztIFZuArsST93OZQWwRgWyJ K433wWxmgcWMEl/uVIHYwgKxEsdvnGUDsVkEVCV+nXgMZvMKeEjsXr6AGeIiOYmlzbUgYU4B T4l9U3aAHSEEVLLvwmYmkL0SAvPYJc5ebGeHmCMg8W3yIRaIXlmJTQeYIY6WlDi44gbLBEbh BYwMqxhFUwuSC4qT0ouM9YoTc4tL89L1kvNzNzECg/v0v2f9OxjvHrA+xCjAwajEw6sRoxom xJpYVlyZe4jRFGjDRGYp0eR8YAzllcQbGpsZWZiamBobmVuaKYnzLpT6GSwkkJ5YkpqdmlqQ WhRfVJqTWnyIkYmDU6qB0Spwb0d/Z+ZcuWVRjsUbH3FvXTjnAP+Xuw+kf2k7nveWdFypNWfa zos5v0xjogJDnD8Inw1Ye+tOE0vyQvt/9QXrz7fM/7M8WjB61ezfJy1Zo9gP3/gdtpgrS1Lj SczHe5Xr0uQNo05ymK1R3HvUluHqededByQtdz19fvHcz80X5RVyeoR+f1NiKc5INNRiLipO BAA7p/dPaQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsVy+t9jQd3d7GphBsv6DC22H3nGavH6haFF 74KrbBabHl9jtbi8aw6bxYzz+5gsXl1axWaxaOsXdouOZYwOnB6bl9R79G1ZxejxeZNcAHNU A6NNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtARSgpl iTmlQKGAxOJiJX07TBNCQ9x0LWAaI3R9Q4LgeowM0EDCGsaMDV3H2QtuWVR0nbzK1MC4Ur+L kZNDQsBEYu+tLywQtpjEhXvr2boYuTiEBGYxSiw4u4kRwmllkph3YxM7SBWbgK7Ek/dzmUFs EYFsiSuN98FsZoHFjBJf7lSB2MICsRLHb5xlA7FZBFQlfp14DGbzCnhI7F6+AKieA2ibnMTS 5lqQMKeAp8S+KTsYQWwhoJJ9FzYzTWDkXcDIsIpRIrUguaA4KT3XKC+1XK84Mbe4NC9dLzk/ dxMjOIqeSe9gPLzL/RCjAAejEg+vZoxqmBBrYllxZe4hRgkOZiURXj02tTAh3pTEyqrUovz4 otKc1OJDjKZAd01klhJNzgdGeF5JvKGxibmpsamliYWJmaWSOO+NQwxhQgLpiSWp2ampBalF MH1MHJxSDYwpPS3nrNU5nc01lQ7tthXerhJwTOHES6/1fLcWBF4xnPBgrZy8sWr8GcbH5+4k rCr5rn4l9fgbz2mfWW7OnrXmWd7DOR+7nq89stn9+puDO2qnPPAImneDs4PxiMoejvMXAxW2 8l7ev6uAy3nN5Da1FY1lzCsnOP3f0CbaISbeGnBcQJ+30K9fiaU4I9FQi7moOBEAcTWDBbgC AAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As now we have dedicated driver for SROM controller, it will take care of saving register banks during S2R so we can safely remove these settings from mach-exynos. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Kconfig | 2 ++ arch/arm/mach-exynos/exynos.c | 17 --------- arch/arm/mach-exynos/include/mach/map.h | 3 -- arch/arm/mach-exynos/regs-srom.h | 53 ---------------------------- arch/arm/mach-exynos/suspend.c | 20 ++--------- arch/arm/plat-samsung/include/plat/map-s5p.h | 1 - 6 files changed, 4 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/mach-exynos/regs-srom.h diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 3a10f1a..62c3139 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -27,6 +27,8 @@ menuconfig ARCH_EXYNOS select SRAM select THERMAL select MFD_SYSCON + select SOC_SAMSUNG + select EXYNOS_SROM if PM help Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 524aa6f..4ffb90e 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -37,11 +37,6 @@ void __iomem *pmu_base_addr; static struct map_desc exynos4_iodesc[] __initdata = { { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), .length = SZ_128K, @@ -64,15 +59,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; -static struct map_desc exynos5_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct platform_device exynos_cpuidle = { .name = "exynos_cpuidle", #ifdef CONFIG_ARM_EXYNOS_CPUIDLE @@ -144,9 +130,6 @@ static void __init exynos_map_io(void) { if (soc_is_exynos4()) iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); - - if (soc_is_exynos5()) - iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); } static void __init exynos_init_io(void) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 86d8085..351e839 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -32,7 +32,4 @@ #define EXYNOS4_PA_COREPERI 0x10500000 #define EXYNOS4_PA_L2CC 0x10502000 -#define EXYNOS4_PA_SROMC 0x12570000 -#define EXYNOS5_PA_SROMC 0x12250000 - #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h deleted file mode 100644 index 5c4d442..0000000 --- a/arch/arm/mach-exynos/regs-srom.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5P SROMC register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_SAMSUNG_REGS_SROM_H -#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__ - -#include - -#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) - -#define S5P_SROM_BW S5P_SROMREG(0x0) -#define S5P_SROM_BC0 S5P_SROMREG(0x4) -#define S5P_SROM_BC1 S5P_SROMREG(0x8) -#define S5P_SROM_BC2 S5P_SROMREG(0xc) -#define S5P_SROM_BC3 S5P_SROMREG(0x10) -#define S5P_SROM_BC4 S5P_SROMREG(0x14) -#define S5P_SROM_BC5 S5P_SROMREG(0x18) - -/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ - -#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 -#define S5P_SROM_BW__ADDRMODE__SHIFT 1 -#define S5P_SROM_BW__WAITENABLE__SHIFT 2 -#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 - -#define S5P_SROM_BW__CS_MASK 0xf - -#define S5P_SROM_BW__NCS0__SHIFT 0 -#define S5P_SROM_BW__NCS1__SHIFT 4 -#define S5P_SROM_BW__NCS2__SHIFT 8 -#define S5P_SROM_BW__NCS3__SHIFT 12 -#define S5P_SROM_BW__NCS4__SHIFT 16 -#define S5P_SROM_BW__NCS5__SHIFT 20 - -/* applies to same to BCS0 - BCS3 */ - -#define S5P_SROM_BCX__PMC__SHIFT 0 -#define S5P_SROM_BCX__TACP__SHIFT 4 -#define S5P_SROM_BCX__TCAH__SHIFT 8 -#define S5P_SROM_BCX__TCOH__SHIFT 12 -#define S5P_SROM_BCX__TACC__SHIFT 16 -#define S5P_SROM_BCX__TCOS__SHIFT 24 -#define S5P_SROM_BCX__TACS__SHIFT 28 - -#endif /* __PLAT_SAMSUNG_REGS_SROM_H */ diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index e00eb39..21abd9b 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -31,12 +31,13 @@ #include #include +#include + #include #include "common.h" #include "exynos-pmu.h" #include "regs-pmu.h" -#include "regs-srom.h" #define REG_TABLE_END (-1U) @@ -52,15 +53,6 @@ struct exynos_wkup_irq { u32 mask; }; -static struct sleep_save exynos_core_save[] = { - /* SROM side */ - SAVE_ITEM(S5P_SROM_BW), - SAVE_ITEM(S5P_SROM_BC0), - SAVE_ITEM(S5P_SROM_BC1), - SAVE_ITEM(S5P_SROM_BC2), - SAVE_ITEM(S5P_SROM_BC3), -}; - struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; @@ -339,8 +331,6 @@ static void exynos_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pm_enter_sleep_mode(); /* ensure at least INFORM0 has the resume address */ @@ -371,8 +361,6 @@ static void exynos5420_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); /* * The cpu state needs to be saved and restored so that the @@ -463,8 +451,6 @@ static void exynos_pm_resume(void) /* For release retention */ exynos_pm_release_retention(); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -531,8 +517,6 @@ static void exynos5420_pm_resume(void) pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - early_wakeup: tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index f5cf2bd..e555769 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -18,7 +18,6 @@ #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) -#define S5P_VA_SROMC S3C_ADDR(0x024C0000) #define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))