From patchwork Tue Oct 20 09:22:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 7444861 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A742CBF90C for ; Tue, 20 Oct 2015 09:23:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C875420861 for ; Tue, 20 Oct 2015 09:23:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A7D020858 for ; Tue, 20 Oct 2015 09:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751257AbbJTJX1 (ORCPT ); Tue, 20 Oct 2015 05:23:27 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:29494 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752156AbbJTJXV (ORCPT ); Tue, 20 Oct 2015 05:23:21 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NWI007U4I2UOS50@mailout2.w1.samsung.com>; Tue, 20 Oct 2015 10:23:18 +0100 (BST) X-AuditID: cbfec7f4-f79c56d0000012ee-a9-562608066ed4 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 7D.F8.04846.60806265; Tue, 20 Oct 2015 10:23:18 +0100 (BST) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NWI005XRI2JNJ70@eusync3.samsung.com>; Tue, 20 Oct 2015 10:23:18 +0100 (BST) From: Andrzej Hajda To: Inki Dae Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Kyungmin Park , dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim , Krzysztof Kozlowski , Sylwester Nawrocki , Hyungwon Hwang Subject: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks Date: Tue, 20 Oct 2015 11:22:32 +0200 Message-id: <1445332961-25419-2-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> References: <1445332961-25419-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDLMWRmVeSWpSXmKPExsVy+t/xq7psHGphBu9ncFrcWneO1WLjjPWs FvOPAFlXvr5ns1g6o4/VYtL9CSwWr18YWvQ/fs1scbbpDbvFx557rBYzzu9jslh75C67xeE3 7awOvB6bVnWyedzvPs7k0bdlFaPH501yASxRXDYpqTmZZalF+nYJXBlP7j5hLfjNW3F84SOW BsYmni5GTg4JAROJaaefMkPYYhIX7q1nA7GFBJYySmxentfFyAVkNzFJ3H78jRUkwSagKfF3 802wIhEBZYlV+9rZQYqYBZ4yS8y9uwEsISwQLTHnZDcLiM0ioCpx78VdRhCbV8BZYvuHF+wQ 2+QkTh6bDDaUU8BFYsuE64wQm50llp9YzjiBkXcBI8MqRtHU0uSC4qT0XEO94sTc4tK8dL3k /NxNjJAw/LKDcfExq0OMAhyMSjy8GjGqYUKsiWXFlbmHGCU4mJVEePXY1MKEeFMSK6tSi/Lj i0pzUosPMUpzsCiJ887d9T5ESCA9sSQ1OzW1ILUIJsvEwSnVwLj4xaUdK//Y3b8Rt9s36IS5 zL29Lo+bo25mBW69zrHNQCt/QvH2HXderbz07N+HlvS0f6HTaxed+P64iu/Kwo9770a/v/Qt L8y0T3bZp4wNh9kPnQi8Zx++a17eo1c1D6dP1jBSu3nNO7nt7JOLn9IdH2038o6V8nt2e2X2 FrafRUsnvPQ/EqM8VYmlOCPRUIu5qDgRALHk+ms/AgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI driver must re-parent respective muxes during HDMI-PHY on/off to HDMI-PHY output clocks. To reference those clocks their definitions should be added. Signed-off-by: Andrzej Hajda --- drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 650ec13..e037406 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, 100000000), /* PHY clocks from HDMI_PHY */ - FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), - FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), + FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", + NULL, CLK_IS_ROOT, 300000000), + FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", + NULL, CLK_IS_ROOT, 166000000), }; static struct samsung_mux_clock disp_mux_clks[] __initdata = { diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 5bd80d5..4f0d566 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -765,7 +765,10 @@ #define CLK_SCLK_RGB_VCLK 109 #define CLK_SCLK_RGB_TV_VCLK 110 -#define DISP_NR_CLK 111 +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 + +#define DISP_NR_CLK 113 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1