From patchwork Mon Nov 2 13:16:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 7536521 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 20C76BF90C for ; Mon, 2 Nov 2015 13:18:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 46620205EA for ; Mon, 2 Nov 2015 13:18:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47EF8205F4 for ; Mon, 2 Nov 2015 13:18:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752776AbbKBNSB (ORCPT ); Mon, 2 Nov 2015 08:18:01 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:43755 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752532AbbKBNSA (ORCPT ); Mon, 2 Nov 2015 08:18:00 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NX600BB9VLXO790@mailout3.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 02 Nov 2015 13:17:58 +0000 (GMT) X-AuditID: cbfec7f5-f794b6d000001495-72-56376285eda6 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 9D.B2.05269.58267365; Mon, 2 Nov 2015 13:17:57 +0000 (GMT) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NX600MT9VLM9S10@eusync4.samsung.com>; Mon, 02 Nov 2015 13:17:57 +0000 (GMT) From: Andrzej Hajda To: Inki Dae Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , Kyungmin Park , linux-samsung-soc@vger.kernel.org, dri-devel@lists.freedesktop.org, Kukjin Kim , Krzysztof Kozlowski Subject: [PATCH 3/7] drm/exynos/hdmi: use array specifier for HDMI-PHY configurations Date: Mon, 02 Nov 2015 14:16:41 +0100 Message-id: <1446470205-15606-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1446470205-15606-1-git-send-email-a.hajda@samsung.com> References: <1446470205-15606-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBLMWRmVeSWpSXmKPExsVy+t/xa7qtSeZhBu8nWVrcWneO1WLjjPWs Fle+vmezmHR/AovF6xeGFv2PXzNbnG16w24x4/w+Jou1R+6yO3B6bFrVyeZxv/s4k0ffllWM Hp83yQWwRHHZpKTmZJalFunbJXBlbDp8l7GgXaZi8TnWBsYV4l2MnBwSAiYS6xfNZYewxSQu 3FvP1sXIxSEksJRR4urWiawQThOTxM0P9xhBqtgENCX+br7JBmKLCChLrNrXzg5SxCxwkUni 7YK3TCAJYYFwiT9P3oCNZRFQlZhz6D2YzSvgLLF7/mdmiHVyEiePTWYFsTkFXCS2fJsPViME VLNw/iOmCYy8CxgZVjGKppYmFxQnpeca6RUn5haX5qXrJefnbmKEhNfXHYxLj1kdYhTgYFTi 4T3gaRYmxJpYVlyZe4hRgoNZSYR3h715mBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHembvehwgJ pCeWpGanphakFsFkmTg4pRoYL8z4W/HF8b9shMnDBdOW3z124H9l4cS+l1L73ppHRQZ7vKzM DJ/sJv5b5G8h240orqxDOw+lrYj8qnFVvIhBZJKG+LT6065vosQ/HmRoW6P7TcHuRpLwG+ny R/zFlk5rj1/6fqHnsvvHml/c206c1Ftcl1cWw2SkLTn5QrGwnbWg/+GlD1xalViKMxINtZiL ihMB2RlrkCsCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI-PHY configurations are stored as array pointer and count pair, we can re-use existing helpers to simplify their initialization. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_hdmi.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 3b92d87..5ff68db 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -90,6 +90,16 @@ static const char * const supply[] = { "vdd_pll", }; +struct hdmiphy_config { + int pixel_clock; + u8 conf[32]; +}; + +struct hdmiphy_configs { + int count; + const struct hdmiphy_config *data; +}; + struct string_array_spec { int count; const char * const *data; @@ -99,9 +109,8 @@ struct string_array_spec { struct hdmi_driver_data { unsigned int type; - const struct hdmiphy_config *phy_confs; - unsigned int phy_conf_count; unsigned int is_apb_phy:1; + struct hdmiphy_configs phy_confs; struct string_array_spec clk_gates; /* * Array of triplets (p_off, p_on, clock), where p_off and p_on are @@ -145,11 +154,6 @@ static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) return container_of(c, struct hdmi_context, connector); } -struct hdmiphy_config { - int pixel_clock; - u8 conf[32]; -}; - /* list of phy config settings */ static const struct hdmiphy_config hdmiphy_v13_configs[] = { { @@ -521,27 +525,24 @@ static const char * const hdmi_clk_muxes4[] = { static const struct hdmi_driver_data exynos5420_hdmi_driver_data = { .type = HDMI_TYPE14, - .phy_confs = hdmiphy_5420_configs, - .phy_conf_count = ARRAY_SIZE(hdmiphy_5420_configs), .is_apb_phy = 1, + .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs), .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), }; static const struct hdmi_driver_data exynos4212_hdmi_driver_data = { .type = HDMI_TYPE14, - .phy_confs = hdmiphy_v14_configs, - .phy_conf_count = ARRAY_SIZE(hdmiphy_v14_configs), .is_apb_phy = 0, + .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs), .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), }; static const struct hdmi_driver_data exynos4210_hdmi_driver_data = { .type = HDMI_TYPE13, - .phy_confs = hdmiphy_v13_configs, - .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs), .is_apb_phy = 0, + .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs), .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), }; @@ -1067,10 +1068,11 @@ static int hdmi_get_modes(struct drm_connector *connector) static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) { + const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs; int i; - for (i = 0; i < hdata->drv_data->phy_conf_count; i++) - if (hdata->drv_data->phy_confs[i].pixel_clock == pixel_clock) + for (i = 0; i < confs->count; i++) + if (confs->data[i].pixel_clock == pixel_clock) return i; DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock); @@ -1611,7 +1613,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) } ret = hdmiphy_reg_write_buf(hdata, 0, - hdata->drv_data->phy_confs[i].conf, 32); + hdata->drv_data->phy_confs.data[i].conf, 32); if (ret) { DRM_ERROR("failed to configure hdmiphy\n"); return;