From patchwork Tue Nov 10 13:23:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 7591031 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 839F8C05CA for ; Tue, 10 Nov 2015 13:25:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8636E20793 for ; Tue, 10 Nov 2015 13:25:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 593EC20708 for ; Tue, 10 Nov 2015 13:25:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753133AbbKJNZI (ORCPT ); Tue, 10 Nov 2015 08:25:08 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:11143 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753112AbbKJNZE (ORCPT ); Tue, 10 Nov 2015 08:25:04 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NXL00JHKP9PIWA0@mailout4.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 10 Nov 2015 13:25:01 +0000 (GMT) X-AuditID: cbfec7f5-f794b6d000001495-56-5641f02d977e Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 2B.B8.05269.D20F1465; Tue, 10 Nov 2015 13:25:01 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NXL00L9RP94NP10@eusync1.samsung.com>; Tue, 10 Nov 2015 13:25:00 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Joonyoung Shim , Seung-Woo Kim , Andrzej Hajda , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Tobias Jakobi , Gustavo Padovan , Javier Martinez Canillas Subject: [PATCH 25/25] drm/exynos: add support for plane scaling Date: Tue, 10 Nov 2015 14:23:41 +0100 Message-id: <1447161821-1877-26-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1447161821-1877-1-git-send-email-m.szyprowski@samsung.com> References: <1447161821-1877-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJLMWRmVeSWpSXmKPExsVy+t/xy7q6HxzDDJqmMFncWneO1WLjjPWs Fle+vmez2PlgF7vFpPsTWCzevF3DZPHi3kUWi9cvDC1mnN/HZLH2yF12ixmTX7JZtK3+wGqx atcfRgdej52z7rJ73O8+zuTx7xi7x5Z+IG/npL1MHn1bVjF6fN4kF8AexWWTkpqTWZZapG+X wJWxddFjpoLNqhUTt69gbmD8L9fFyMEhIWAi8fSofRcjJ5ApJnHh3nq2LkYuDiGBpYwSk/tW sUA4TUwSxyc/ZAWpYhMwlOh628UGYosIuEk0HZ4JFmcWOMwscXhqHYgtLOAgcXvmG7A4i4Cq xMO/fxhBbF4BD4mlJ9exQWyTk/j/cgUTiM0JFN/68TMziC0k4C5xs+kiywRG3gWMDKsYRVNL kwuKk9JzjfSKE3OLS/PS9ZLzczcxQgL06w7GpcesDjEKcDAq8fBO+OYQJsSaWFZcmXuIUYKD WUmEl/G1Y5gQb0piZVVqUX58UWlOavEhRmkOFiVx3pm73ocICaQnlqRmp6YWpBbBZJk4OKUa GFPUsw8vir55/8VSxw32rYd4LrDMuWekcKKmpreotUD/YMvHS0u/6r+au6HQvuf6hIa1fh0q E+Zf6FjCfDbvuGtA/EabO1fLb7XuMHBtEBO8z/Xws6GKzKX0XTJ/Gj7MX9DHdHRX7M+XSdut 657y/0lhU+3y01t7xe0274rOAg4DiZ/b7NbH9CqxFGckGmoxFxUnAgAeoMCYTAIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for plane scaling. Minor changes were needed to use existing Exynos IPP integration code for enabling scaling feature. Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_drm_plane.c | 8 +++++--- drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c | 22 ++++++++++++++++++++-- drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h | 8 ++++++-- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index e24285b148c2..0d0c451b4f6b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -57,7 +57,8 @@ static int exynos_plane_get_size(int start, unsigned length, unsigned last) return size; } -static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) +static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state, + const struct exynos_drm_plane_config *config) { struct drm_plane_state *state = &exynos_state->base; @@ -86,7 +87,8 @@ static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state) src_w = state->src_w >> 16; src_h = state->src_h >> 16; - exynos_plane_ipp_setup(exynos_state, &src_x, &src_y, &src_w, &src_h); + exynos_plane_ipp_setup(exynos_state, config, &src_x, &src_y, &src_w, + &src_h, &crtc_w, &crtc_h); /* set ratio */ exynos_state->h_ratio = (src_w << 16) / crtc_w; @@ -245,7 +247,7 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, return 0; /* translate state into exynos_state */ - exynos_plane_mode_set(exynos_state); + exynos_plane_mode_set(exynos_state, exynos_plane->config); ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state); if (ret) diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c index 126d0bde2ccf..2d12eb391262 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.c @@ -121,15 +121,24 @@ static int exynos_plane_ipp_transform(struct exynos_drm_plane_state *state) } void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, unsigned int *src_x, unsigned int *src_y, - unsigned int *src_w, unsigned int *src_h) + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h) { int rotation = state->base.rotation; int pre_x, pre_y, post_x, post_y; state->rotation = rotation; - if (rotation == 0 || rotation == BIT(DRM_ROTATE_0)) + /* check if ipp is really needed */ + if (rotation == BIT(DRM_ROTATE_0) && + (*src_w == *crtc_w || + ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE_X) && + *src_w * 2 == *crtc_w)) && + (*src_h == *crtc_h || + ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE_Y) && + *src_h * 2 == *crtc_h))) return; state->ipp_needed = true; @@ -183,6 +192,15 @@ void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, swap(state->ipp_dst.w, state->ipp_dst.h); break; } + + /* apply scalling */ + state->ipp_dst.w = state->ipp_dst.w * *crtc_w / *src_w; + state->ipp_dst.h = state->ipp_dst.h * *crtc_h / *src_h; + + *src_x = *src_x * *crtc_w / *src_w; + *src_y = *src_y * *crtc_h / *src_h; + *src_w = *crtc_w; + *src_h = *crtc_h; } int exynos_plane_ipp_check(struct exynos_drm_plane *plane, diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h index defb4f95e075..1709bb1a26e4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h +++ b/drivers/gpu/drm/exynos/exynos_drm_plane_ipp.h @@ -15,8 +15,10 @@ #ifdef CONFIG_DRM_EXYNOS_PLANE_IPP void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, unsigned int *src_x, unsigned int *src_y, - unsigned int *src_w, unsigned int *src_h); + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h); int exynos_plane_ipp_check(struct exynos_drm_plane *plane, struct exynos_drm_plane_state *state); @@ -34,8 +36,10 @@ int exynos_plane_ipp_attach_properties(struct drm_device *dev, static inline void exynos_plane_ipp_setup(struct exynos_drm_plane_state *state, + const struct exynos_drm_plane_config *config, unsigned int *src_x, unsigned int *src_y, - unsigned int *src_w, unsigned int *src_h) + unsigned int *src_w, unsigned int *src_h, + unsigned int *crtc_w, unsigned int *crtc_h) { }