From patchwork Sun Nov 22 16:09:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tobias Jakobi X-Patchwork-Id: 7676451 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2A8CBBF90C for ; Sun, 22 Nov 2015 16:10:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 57C6C20647 for ; Sun, 22 Nov 2015 16:10:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AFEF92063D for ; Sun, 22 Nov 2015 16:10:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752427AbbKVQKv (ORCPT ); Sun, 22 Nov 2015 11:10:51 -0500 Received: from smtp.math.uni-bielefeld.de ([129.70.45.10]:45604 "EHLO smtp.math.uni-bielefeld.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752138AbbKVQKu (ORCPT ); Sun, 22 Nov 2015 11:10:50 -0500 Received: from chidori.local (dslb-092-077-040-173.092.077.pools.vodafone-ip.de [92.77.40.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client did not present a certificate) by smtp.math.uni-bielefeld.de (Postfix) with ESMTPSA id B985C6004D; Sun, 22 Nov 2015 17:10:48 +0100 (CET) From: Tobias Jakobi To: linux-samsung-soc@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, m.szyprowski@samsung.com, gustavo.padovan@collabora.co.uk, jy0922.shim@samsung.com, inki.dae@samsung.com, Tobias Jakobi Subject: [PATCH v2 4/5] drm/exynos: mixer: do blending setup in mixer_cfg_layer() Date: Sun, 22 Nov 2015 17:09:43 +0100 Message-Id: <1448208584-6621-5-git-send-email-tjakobi@math.uni-bielefeld.de> X-Mailer: git-send-email 2.4.9 In-Reply-To: <1448208584-6621-1-git-send-email-tjakobi@math.uni-bielefeld.de> References: <1448208584-6621-1-git-send-email-tjakobi@math.uni-bielefeld.de> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This updates the blending setup when the layer configuration changes (triggered by mixer_win_{commit,disable}). To avoid unnecesary reconfigurations we cache the layer state in the mixer context. Extra care has to be taken for the layer that is currently being enabled/disabled. Signed-off-by: Tobias Jakobi --- drivers/gpu/drm/exynos/exynos_mixer.c | 41 +++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index ec9659e..1c24fb5 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -99,6 +99,7 @@ struct mixer_context { struct exynos_drm_plane planes[MIXER_WIN_NR]; const struct layer_cfg *layer_cfg; unsigned int num_layer; + u32 layer_state; int pipe; unsigned long flags; bool interlace; @@ -189,6 +190,27 @@ static inline bool is_alpha_format(const struct mixer_context* ctx, unsigned int } } +static inline u32 get_layer_state(const struct mixer_context *ctx, + unsigned int win, bool enable) +{ + u32 enable_state, alpha_state; + + enable_state = ctx->layer_state & 0xffff; + alpha_state = ctx->layer_state >> 16; + + if (enable) + enable_state |= (1 << win); + else + enable_state &= ~(1 << win); + + if (enable && is_alpha_format(ctx, win)) + alpha_state |= (1 << win); + else + alpha_state &= ~(1 << win); + + return ((alpha_state << 16) | enable_state); +} + static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) { return readl(res->vp_regs + reg_id); @@ -370,8 +392,9 @@ static void mixer_general_layer(struct mixer_context *ctx, { u32 val; struct mixer_resources *res = &ctx->mixer_res; + const u32 alpha_state = ctx->layer_state >> 16; - if (is_alpha_format(ctx, cfg->index)) { + if (alpha_state & (1 << cfg->index)) { val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ val |= MXR_GRP_CFG_BLEND_PRE_MUL; val |= MXR_GRP_CFG_PIXEL_BLEND_EN; /* blending based on pixel alpha */ @@ -397,10 +420,11 @@ static void mixer_general_layer(struct mixer_context *ctx, } } -static void mixer_layer_blending(struct mixer_context *ctx, unsigned int enable_state) +static void mixer_layer_blending(struct mixer_context *ctx) { unsigned int i, index; bool bottom_layer = false; + const u32 enable_state = ctx->layer_state & 0xffff; for (i = 0; i < ctx->num_layer; ++i) { index = ctx->layer_cfg[i].index; @@ -503,8 +527,19 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, bool enable) { struct mixer_resources *res = &ctx->mixer_res; + u32 new_layer_state; u32 val = enable ? ~0 : 0; + new_layer_state = get_layer_state(ctx, win, enable); + if (new_layer_state == ctx->layer_state) + return; + + /* + * Update the layer state so that mixer_layer_blending() + * below can use it. + */ + ctx->layer_state = new_layer_state; + switch (win) { case 0: mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); @@ -520,6 +555,8 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, } break; } + + mixer_layer_blending(ctx); } static void mixer_run(struct mixer_context *ctx)