@@ -700,6 +700,40 @@
clock-names = "ppmu";
status = "disabled";
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <133000000>;
+ opp-microvolt = <800000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <875000>;
+ };
+ };
};
};
This patch adds the DMC (DRAM memory controller) bus node for Exynos3250 SoC. The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard SDRAM devices. The bus includes the OPP tables and the source clock for DMC block. Following list specifies the detailed relation between the clock and DMC block: - The source clock of DMC block : div_dmc Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)