From patchwork Wed Dec 2 21:19:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Gamari X-Patchwork-Id: 7753191 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3E4A4BEEE1 for ; Wed, 2 Dec 2015 21:31:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5463B2053F for ; Wed, 2 Dec 2015 21:31:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 69D5F20546 for ; Wed, 2 Dec 2015 21:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932204AbbLBV3a (ORCPT ); Wed, 2 Dec 2015 16:29:30 -0500 Received: from mail.smart-cactus.org ([54.187.36.80]:50830 "EHLO mail.smart-cactus.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757054AbbLBV32 (ORCPT ); Wed, 2 Dec 2015 16:29:28 -0500 Received: from localhost.localdomain (HSI-KBW-149-172-43-78.hsi13.kabel-badenwuerttemberg.de [149.172.43.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client did not present a certificate) (Authenticated sender: ben@smart-cactus.org) by mail.smart-cactus.org (Postfix) with ESMTPSA id 7809764B60; Wed, 2 Dec 2015 21:07:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mail.smart-cactus.org; s=mail; t=1449090463; bh=UCtllEP3qAZrBh8P9+C7dzsXy8fFqQQEAUQvJHwAJCQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I7hKjjLZpePLC/qqSYJ6RjOWgoIvriNIONcOobxQvOYSbcTaxDV/eq0a5R79tWnQO P/weQNdWdT2YvilwPIiFiIQqYg0ShM1sL9jlaNRnFZbAXkwtOp2Ok2Anu/JZwqV8+O qCMSuEbtFGc7gYOFukcbAuRpLhfnV69TtKqVoGvQ= From: Ben Gamari To: Thomas Abraham , Sylwester Nawrocki , Michael Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com, Mike Turquette , Javier Martinez Canillas , Ben Gamari Subject: [PATCH 05/12] clk: samsung: exynos5800: fix cpu clock configuration data Date: Wed, 2 Dec 2015 22:19:20 +0100 Message-Id: <1449091167-20758-6-git-send-email-ben@smart-cactus.org> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1449091167-20758-1-git-send-email-ben@smart-cactus.org> References: <1449091167-20758-1-git-send-email-ben@smart-cactus.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartlomiej Zolnierkiewicz Fix cpu clock configuration data for Exynos5800 (it uses higher PCLK_DBG divider values than Exynos5420 and supports additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Cc: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Ben Gamari --- drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 2288052..aa44bb7 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 0 }, +}; + #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ { 1300000, E5420_KFC_DIV(3, 5, 2), }, { 1200000, E5420_KFC_DIV(3, 5, 2), }, { 1100000, E5420_KFC_DIV(3, 5, 2), }, @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", - mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + if (soc == EXYNOS5420) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); + } exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);