From patchwork Mon Dec 7 18:18:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 7788781 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2D903BEEE1 for ; Mon, 7 Dec 2015 18:21:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 404E72054B for ; Mon, 7 Dec 2015 18:21:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 40348204F6 for ; Mon, 7 Dec 2015 18:21:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932084AbbLGSVC (ORCPT ); Mon, 7 Dec 2015 13:21:02 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:58480 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932711AbbLGSUU (ORCPT ); Mon, 7 Dec 2015 13:20:20 -0500 Received: from epcpsbgm2new.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ001STF2XRQ480@mailout3.samsung.com>; Tue, 08 Dec 2015 03:20:18 +0900 (KST) X-AuditID: cbfee61b-f793c6d00000236c-32-5665cde2ce1f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 96.3D.09068.2EDC5665; Tue, 8 Dec 2015 03:20:18 +0900 (KST) Received: from AMDC1976.DIGITAL.local ([106.120.53.102]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ000I0K2W6PR40@mmp2.samsung.com>; Tue, 08 Dec 2015 03:20:18 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Ben Gamari Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables Date: Mon, 07 Dec 2015 19:18:19 +0100 Message-id: <1449512300-17230-8-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> References: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrILMWRmVeSWpSXmKPExsVy+t9jQd1HZ1PDDNb81rbYOGM9q8Ws+XdZ LK5/ec5q8f/Ra1aLN2/XMFm8fmFo0bvgKptF/+PXzBZfD69gtHjzcDOjxabH11gtLu+aw2bx ufcIo8WM8/uYLNZtvMVu8XTCRTaLw2/aWS06ljFatK3+wGqxatcfRouNXz0cRD12zrrL7rFp VSebx51re9g8Ni+p9/h3jN1jSz9QuG/LKkaPM7+dPbZfm8fs8XmTXABXFJdNSmpOZllqkb5d AlfGk5OtLAVLRSrWdrezNTBuE+hi5OSQEDCRuHj7BxOELSZx4d56ti5GLg4hgVmMEis6VrJC OL8YJR7svcQMUsUmYCUxsX0VI0hCROAYk8Sj1pvsIA6zwGtmiaMH/4LNEhawkZi76DbQLA4O FgFViQ8dySBhXgEPiTkXT7BDrJOTOHlsMiuIzSngKXHl7TowWwioZuX2l6wTGHkXMDKsYpRI LUguKE5KzzXKSy3XK07MLS7NS9dLzs/dxAiOiGfSOxgP73I/xCjAwajEw3viWGqYEGtiWXFl 7iFGCQ5mJRFe2UygEG9KYmVValF+fFFpTmrxIUZpDhYlcd59lyLDhATSE0tSs1NTC1KLYLJM HJxSDYw7L/EvCrqomWrHm/RkCj9zafC69VbXQla/efjwtIm95N5g7sCp0h3rXi3ckXdj0v3J u7ytZXN/Bx6XEfx932V2U3XOn34Zg11v+HfX78tx35f5Pbzn35ksGUn+yzver3ez8340o1/J cu2T6oBPd+Uf7i/566Zw2oPXeFZ3xqNDkm49x9IPfXVQYinOSDTUYi4qTgQA/UScq4QCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Gamari The Exynos 5422 is identical to the 5800 except for the fact that it boots from the A7 cores. Consequently, the core numbering is different: cores 0-3 are A7s whereas 4-7 are A15s. We can reuse the device tree of the 5800 for the 5422 but we must take care to override the OPP tables and CPU clocks. These are otherwise inherited from the exynos5800 devicetree, which has the CPU clusters reversed compared to the 5422. This results in the A15 cores only reaching 1.4GHz, the maximum rate of the KFC clock. Cc: Javier Martinez Canillas Signed-off-by: Ben Gamari Signed-off-by: Bartlomiej Zolnierkiewicz --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index b7f60c8..9a5131d 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -20,8 +20,10 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu1 { @@ -30,6 +32,7 @@ reg = <0x101>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu2 { @@ -38,6 +41,7 @@ reg = <0x102>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu3 { @@ -46,14 +50,17 @@ reg = <0x103>; clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; + operating-points-v2 = <&cpu1_opp_table>; }; &cpu4 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; + clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu5 { @@ -62,6 +69,7 @@ reg = <0x1>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu6 { @@ -70,6 +78,7 @@ reg = <0x2>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; }; &cpu7 { @@ -78,4 +87,5 @@ reg = <0x3>; clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; + operating-points-v2 = <&cpu0_opp_table>; };