From patchwork Tue Dec 8 13:46:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 7797691 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4EEBEBEEE1 for ; Tue, 8 Dec 2015 13:47:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7DB3D204B5 for ; Tue, 8 Dec 2015 13:47:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 959D820453 for ; Tue, 8 Dec 2015 13:47:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756340AbbLHNrb (ORCPT ); Tue, 8 Dec 2015 08:47:31 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:16611 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756396AbbLHNrO (ORCPT ); Tue, 8 Dec 2015 08:47:14 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ100DQSKYN43A0@mailout1.w1.samsung.com>; Tue, 08 Dec 2015 13:47:11 +0000 (GMT) X-AuditID: cbfec7f4-f79026d00000418a-5c-5666df5f1570 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 8F.75.16778.F5FD6665; Tue, 8 Dec 2015 13:47:11 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ1001MIKYJFT20@eusync4.samsung.com>; Tue, 08 Dec 2015 13:47:11 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Krzysztof Kozlowski , Kukjin Kim Subject: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks Date: Tue, 08 Dec 2015 14:46:54 +0100 Message-id: <1449582415-30164-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLJMWRmVeSWpSXmKPExsVy+t/xa7rx99PCDI7sZLd4/cLQov/xa2aL y7vmsFnMOL+PyWLtkbvsFhdPuVocftPOarFq1x9GBw6P9zda2T12zrrL7rFpVSebR9+WVYwe nzfJBbBGcdmkpOZklqUW6dslcGVsnLSWtWC1QEXD33csDYz/eLsYOTkkBEwkvmzewAphi0lc uLeeDcQWEljKKHH6sFMXIxeQ3cQkMevjErAEm4ChRNfbLjBbRMBZomFqIxOIzSzwn1Fi0WtH EFtYIFTi0NqzYHEWAVWJLYcWMnYxcnDwCnhInH4eDLFLTuL/yxVMExi5FzAyrGIUTS1NLihO Ss811CtOzC0uzUvXS87P3cQICZQvOxgXH7M6xCjAwajEw3viWGqYEGtiWXFl7iFGCQ5mJRHe vHtpYUK8KYmVValF+fFFpTmpxYcYpTlYlMR55+56HyIkkJ5YkpqdmlqQWgSTZeLglGpg5Fig 86G5d8vfBZ68L6XPfax5E/9v4bXHYX0fdmbuSbA+6Nfep37YdNf6FVorXdYJ2Phq+d5YX6PM Pz9ntuLHM7MyZ+5XOuXT/U1IJSPz+f7QFuWd7QHqBqpOhsYh6TJPeJ2sJLxVJ7cFVdcVfGp5 rnFr0crN8h2cjjdz9mysXCDL4TRz6/tbSizFGYmGWsxFxYkATiKnUhACAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds clocks, which are required for preserving parent clock configuration on GSCL power domain on/off. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Acked-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos5420.c | 8 ++++---- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 389af3c..4bae2e3 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -677,8 +677,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP5, 20, 1), MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), - MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, - SRC_TOP5, 28, 1), + MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", + mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), @@ -729,8 +729,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), - MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, - SRC_TOP12, 28, 1), + MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", + mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), /* DISP1 Block */ MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 99da0d1..b5af23a 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -210,6 +210,8 @@ #define CLK_MOUT_SW_ACLK300 649 #define CLK_MOUT_USER_ACLK400_DISP1 650 #define CLK_MOUT_SW_ACLK400 651 +#define CLK_MOUT_USER_ACLK300_GSCL 652 +#define CLK_MOUT_SW_ACLK300_GSCL 653 /* divider clocks */ #define CLK_DOUT_PIXEL 768