From patchwork Wed Dec 9 04:08:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7804341 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5F9C7BEEE1 for ; Wed, 9 Dec 2015 04:15:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6F12B20386 for ; Wed, 9 Dec 2015 04:15:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5E61020490 for ; Wed, 9 Dec 2015 04:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753304AbbLIEJa (ORCPT ); Tue, 8 Dec 2015 23:09:30 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:59296 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753033AbbLIEIa (ORCPT ); Tue, 8 Dec 2015 23:08:30 -0500 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ201OK6OTTBCC0@mailout1.samsung.com>; Wed, 09 Dec 2015 13:08:17 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.115]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 11.1D.04886.139A7665; Wed, 9 Dec 2015 13:08:17 +0900 (KST) X-AuditID: cbfee690-f79646d000001316-eb-5667a931e1a9 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 99.77.13906.139A7665; Wed, 9 Dec 2015 13:08:17 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ200G00OTQA230@mmp2.samsung.com>; Wed, 09 Dec 2015 13:08:17 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Wed, 09 Dec 2015 13:08:06 +0900 Message-id: <1449634091-1842-15-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWyRsSkWNdwZXqYwaV3UhbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C0u75rDZvG59wijxYzz+5gs1m28xW5x+zKvxdLr F5ksbjeuYLOYMH0ti0Xr3iPsFm2rP7A6CHqsmbeG0aOluYfN43JfL5PHzll32T1WLv/C5rFp VSebx79j7B59W1YxenzeJBfAGcVlk5Kak1mWWqRvl8CV8fT6QpaCr9IVT2c+Z2pg/C3axcjB ISFgIrHlgXcXIyeQKSZx4d56ti5GLg4hgRWMEg1X21hhatY/zIGIz2KU+PT7LjOE84VR4uyD w6wg3WwCWhL7X9xgA7FFBNwlvt7bDTaJWeALk0Tr5O/MIAlhAT+Jd9eXMoLYLAKqEid+dbCA 2LwCrhKr/85khThDTuLDnkfsIDYnUPzK9ndg9UICLhLHnjYxgQyVEGjlkPjb8YoFYpCAxLfJ h1ggTpWV2HSAGWKOpMTBFTdYJjAKL2BkWMUomlqQXFCclF5kolecmFtcmpeul5yfu4kRGG2n /z2bsIPx3gHrQ4wCHIxKPLwXXNLDhFgTy4orcw8xmgJtmMgsJZqcD4zpvJJ4Q2MzIwtTE1Nj I3NLMyVx3tdSP4OFBNITS1KzU1MLUovii0pzUosPMTJxcEo1MCYZVe1RcZbqDbNokv9mZvt8 5e/k7ZsrDr9Rrmy9fe7j4a03tOfsN/ulHBHyMj14ZtSq9LWf817JeKxZYqDTlOq2Z42yuonQ 8w9Prof8rL8nc7R2TbRU/xkxbltlbo7Zj/+JrJvm6h1uWl0iM2n2ApEdRpzqOjPsO0w58s/N ql1aY7ussLlRSImlOCPRUIu5qDgRANu4fhSxAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsVy+t9jQV3DlelhBlOaRS2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZrNt4i93i9mVei6XX LzJZ3G5cwWYxYfpaFovWvUfYLdpWf2B1EPRYM28No0dLcw+bx+W+XiaPnbPusnusXP6FzWPT qk42j3/H2D36tqxi9Pi8SS6AM6qB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJc SSEvMTfVVsnFJ0DXLTMH6BUlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGEN Y8bT6wtZCr5KVzyd+ZypgfG3aBcjB4eEgInE+oc5XYycQKaYxIV769m6GLk4hARmMUp8+n2X GcL5wihx9sFhVpAqNgEtif0vbrCB2CIC7hJf7+0G62AW+MIk0Tr5OzNIQljAT+Ld9aWMIDaL gKrEiV8dLCA2r4CrxOq/M1kh1slJfNjziB3E5gSKX9n+DqxeSMBF4tjTJqYJjLwLGBlWMUqk FiQXFCel5xrmpZbrFSfmFpfmpesl5+duYgTH9DOpHYwHd7kfYhTgYFTi4b3gkh4mxJpYVlyZ e4hRgoNZSYRXqxYoxJuSWFmVWpQfX1Sak1p8iNEU6LCJzFKiyfnAdJNXEm9obGJmZGlkbmhh ZGyuJM5beykyTEggPbEkNTs1tSC1CKaPiYNTqoFR7eyzLEHrv2xJ837v/h8zr9Du+/+9cz+v i3me87RJQUbsdEbKVjsvtWjrgxGvTD5rSZ805J/oecUu8n6MVJbKpZ9aJ//bB23t+nL++Kxl ddMf3dj453T0Ka8T3V/nruH5xhk7YY/15kQOkay+M3LLlpxfET5FdNvH6Jcee4Iq1r2MebT4 fqPPdyWW4oxEQy3mouJEADYHTlH/AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus noes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 3bcf0939755e..8bc4aee156b5 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -354,6 +354,118 @@ opp-microvolt = <950000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp02 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp01 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <925000>; + }; + }; }; &combiner {