From patchwork Sat Dec 12 07:44:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 7834341 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 72322BEEE1 for ; Sat, 12 Dec 2015 07:49:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6937B203AE for ; Sat, 12 Dec 2015 07:49:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2762420266 for ; Sat, 12 Dec 2015 07:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751960AbbLLHs2 (ORCPT ); Sat, 12 Dec 2015 02:48:28 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:35895 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751562AbbLLHr6 (ORCPT ); Sat, 12 Dec 2015 02:47:58 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ8008XCIZW0490@mailout4.samsung.com>; Sat, 12 Dec 2015 16:47:56 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.123]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 71.75.04949.C21DB665; Sat, 12 Dec 2015 16:47:56 +0900 (KST) X-AuditID: cbfee68d-f79646d000001355-45-566bd12cff6e Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id E8.78.09068.C21DB665; Sat, 12 Dec 2015 16:47:56 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZ800L1WIYL6X10@mmp1.samsung.com>; Sat, 12 Dec 2015 16:47:56 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, thomas.ab@samsung.com, p.fedin@samsung.com, andi.shyti@samsung.com, Pankaj Dubey , Kukjin Kim Subject: [RESEND PATCH v5 8/8] ARM: EXYNOS: Remove SROM related register settings from mach-exynos Date: Sat, 12 Dec 2015 13:14:02 +0530 Message-id: <1449906242-20843-9-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.4.5 In-reply-to: <1449906242-20843-1-git-send-email-pankaj.dubey@samsung.com> References: <1449906242-20843-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWyRsSkWlfnYnaYwdljyhbbjzxjtXj9wtCi d8FVNov+x6+ZLTY9vsZqcXnXHDaLGef3MVm8urSKzWLR1i/sFh3LGB24PDat6mTz2Lyk3qNv yypGj8+b5AJYorhsUlJzMstSi/TtErgytl/4wVLwx6pi9e9ZjA2Mcwy7GDk5JARMJH6d6mSH sMUkLtxbzwZiCwmsYJRoP5YCU9O5qoG5i5ELKL6UUWL/1v+sEE4rk8Sdhi6wDjYBXYkn7+cy g9giAtkSVxrvg3UwCxxilJhz+RwLSEJYIEXiy+n9YOtYBFQlNs3ZBtbAK+Ah8X3RAqA4B9A6 OYmlzbUgYU4BT4lbOzpZIC7ykNhzsZMRZKaEwCp2iSv3m9gg5ghIfJt8iAWiV1Zi0wFmiKsl JQ6uuMEygVF4ASPDKkbR1ILkguKk9CJDveLE3OLSvHS95PzcTYzAoD/971nvDsbbB6wPMQpw MCrx8FrkZ4cJsSaWFVfmHmI0BdowkVlKNDkfGFt5JfGGxmZGFqYmpsZG5pZmSuK8ilI/g4UE 0hNLUrNTUwtSi+KLSnNSiw8xMnFwSjUwmgnMfGjO1MvFO0t8uXS8jlyMvqizgeCmyRtCttZM ri05uvj71XemsYafJ/MtvvmtYda9Jc2Z69oXtVyqMWy5JPPKTXdilfbnXeVPd4oneugXfH2a 2Nw9Q/vVvIenlaqt/559kPDPcpF4ZOjB/N3f9m/JjdleOakjoOWVTfSk9WtvKap+KLbQVmIp zkg01GIuKk4EAO0ePwF1AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsVy+t9jAV2di9lhBmsvS1tsP/KM1eL1C0OL 3gVX2Sz6H79mttj0+BqrxeVdc9gsZpzfx2Tx6tIqNotFW7+wW3QsY3Tg8ti0qpPNY/OSeo++ LasYPT5vkgtgiWpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBOkdJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmLH9wg+Wgj9W Fat/z2JsYJxj2MXIySEhYCLRuaqBGcIWk7hwbz1bFyMXh5DAUkaJ/Vv/s0I4rUwSdxq62ECq 2AR0JZ68nwvWISKQLXGl8T4zSBGzwCFGiTmXz7GAJIQFUiS+nN7PDmKzCKhKbJqzDayBV8BD 4vuiBUBxDqB1chJLm2tBwpwCnhK3dnSCtQoBley52Mk4gZF3ASPDKkaJ1ILkguKk9FyjvNRy veLE3OLSvHS95PzcTYzg2HomvYPx8C73Q4wCHIxKPLwPcrLDhFgTy4orc4Hu4WBWEuENLwUK 8aYkVlalFuXHF5XmpBYfYjQFumsis5Rocj4w7vNK4g2NTcxNjU0tTSxMzCyVxHn3XYoMExJI TyxJzU5NLUgtgulj4uCUamCsFesyOxxwY4KyY1LW2Ry3jx8ef150W0kyO0VdUTwiU6H3R2Px 12nvFph/ENvzQaTx+KxUz9SVTHcWCClkhG/dwGxlNuWD2fVZu0zKrjuEXg9lUuL8655+5pma 6dOnMa5bzVWuc+95m9dwrTMoSanNYP/ZbysfP9bxz7uypt9A8oH4O8MPKWeVWIozEg21mIuK EwGNUYJ0wwIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As now we have dedicated driver for SROM controller, it will take care of saving register banks during S2R so we can safely remove these settings from mach-exynos. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/Kconfig | 2 ++ arch/arm/mach-exynos/exynos.c | 17 --------- arch/arm/mach-exynos/include/mach/map.h | 3 -- arch/arm/mach-exynos/regs-srom.h | 53 ---------------------------- arch/arm/mach-exynos/suspend.c | 20 ++--------- arch/arm/plat-samsung/include/plat/map-s5p.h | 1 - 6 files changed, 4 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/mach-exynos/regs-srom.h diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 3a10f1a..83c85f5 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -16,6 +16,7 @@ menuconfig ARCH_EXYNOS select ARM_GIC select COMMON_CLK_SAMSUNG select EXYNOS_THERMAL + select EXYNOS_SROM if PM select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -24,6 +25,7 @@ menuconfig ARCH_EXYNOS select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC + select SOC_SAMSUNG select SRAM select THERMAL select MFD_SYSCON diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 524aa6f..4ffb90e 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -37,11 +37,6 @@ void __iomem *pmu_base_addr; static struct map_desc exynos4_iodesc[] __initdata = { { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), .length = SZ_128K, @@ -64,15 +59,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; -static struct map_desc exynos5_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct platform_device exynos_cpuidle = { .name = "exynos_cpuidle", #ifdef CONFIG_ARM_EXYNOS_CPUIDLE @@ -144,9 +130,6 @@ static void __init exynos_map_io(void) { if (soc_is_exynos4()) iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); - - if (soc_is_exynos5()) - iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); } static void __init exynos_init_io(void) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 86d8085..351e839 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -32,7 +32,4 @@ #define EXYNOS4_PA_COREPERI 0x10500000 #define EXYNOS4_PA_L2CC 0x10502000 -#define EXYNOS4_PA_SROMC 0x12570000 -#define EXYNOS5_PA_SROMC 0x12250000 - #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h deleted file mode 100644 index 5c4d442..0000000 --- a/arch/arm/mach-exynos/regs-srom.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5P SROMC register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_SAMSUNG_REGS_SROM_H -#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__ - -#include - -#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) - -#define S5P_SROM_BW S5P_SROMREG(0x0) -#define S5P_SROM_BC0 S5P_SROMREG(0x4) -#define S5P_SROM_BC1 S5P_SROMREG(0x8) -#define S5P_SROM_BC2 S5P_SROMREG(0xc) -#define S5P_SROM_BC3 S5P_SROMREG(0x10) -#define S5P_SROM_BC4 S5P_SROMREG(0x14) -#define S5P_SROM_BC5 S5P_SROMREG(0x18) - -/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ - -#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 -#define S5P_SROM_BW__ADDRMODE__SHIFT 1 -#define S5P_SROM_BW__WAITENABLE__SHIFT 2 -#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 - -#define S5P_SROM_BW__CS_MASK 0xf - -#define S5P_SROM_BW__NCS0__SHIFT 0 -#define S5P_SROM_BW__NCS1__SHIFT 4 -#define S5P_SROM_BW__NCS2__SHIFT 8 -#define S5P_SROM_BW__NCS3__SHIFT 12 -#define S5P_SROM_BW__NCS4__SHIFT 16 -#define S5P_SROM_BW__NCS5__SHIFT 20 - -/* applies to same to BCS0 - BCS3 */ - -#define S5P_SROM_BCX__PMC__SHIFT 0 -#define S5P_SROM_BCX__TACP__SHIFT 4 -#define S5P_SROM_BCX__TCAH__SHIFT 8 -#define S5P_SROM_BCX__TCOH__SHIFT 12 -#define S5P_SROM_BCX__TACC__SHIFT 16 -#define S5P_SROM_BCX__TCOS__SHIFT 24 -#define S5P_SROM_BCX__TACS__SHIFT 28 - -#endif /* __PLAT_SAMSUNG_REGS_SROM_H */ diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index c169cc3..237653e 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -32,12 +32,13 @@ #include #include +#include + #include #include "common.h" #include "exynos-pmu.h" #include "regs-pmu.h" -#include "regs-srom.h" #define REG_TABLE_END (-1U) @@ -53,15 +54,6 @@ struct exynos_wkup_irq { u32 mask; }; -static struct sleep_save exynos_core_save[] = { - /* SROM side */ - SAVE_ITEM(S5P_SROM_BW), - SAVE_ITEM(S5P_SROM_BC0), - SAVE_ITEM(S5P_SROM_BC1), - SAVE_ITEM(S5P_SROM_BC2), - SAVE_ITEM(S5P_SROM_BC3), -}; - struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; @@ -343,8 +335,6 @@ static void exynos_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pm_enter_sleep_mode(); /* ensure at least INFORM0 has the resume address */ @@ -375,8 +365,6 @@ static void exynos5420_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); /* * The cpu state needs to be saved and restored so that the @@ -467,8 +455,6 @@ static void exynos_pm_resume(void) /* For release retention */ exynos_pm_release_retention(); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -535,8 +521,6 @@ static void exynos5420_pm_resume(void) pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - early_wakeup: tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index f5cf2bd..e555769 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -18,7 +18,6 @@ #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) -#define S5P_VA_SROMC S3C_ADDR(0x024C0000) #define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))