From patchwork Mon Dec 14 06:38:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7841811 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8D5ABBEEE1 for ; Mon, 14 Dec 2015 06:44:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A9EE620456 for ; Mon, 14 Dec 2015 06:44:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6D62A2054B for ; Mon, 14 Dec 2015 06:44:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752672AbbLNGit (ORCPT ); Mon, 14 Dec 2015 01:38:49 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:53134 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752592AbbLNGii (ORCPT ); Mon, 14 Dec 2015 01:38:38 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZC02PFX54CP6A0@mailout4.samsung.com>; Mon, 14 Dec 2015 15:38:36 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 3C.7F.04964.CE36E665; Mon, 14 Dec 2015 15:38:36 +0900 (KST) X-AuditID: cbfee68f-f793a6d000001364-97-566e63ec74bd Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 3C.0E.09068.BE36E665; Mon, 14 Dec 2015 15:38:36 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZC00FY8541SY80@mmp2.samsung.com>; Mon, 14 Dec 2015 15:38:35 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver Date: Mon, 14 Dec 2015 15:38:06 +0900 Message-id: <1450075104-13705-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> References: <1450075104-13705-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWyRsSkUPdNcl6YwbXF7BbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C0u75rDZvG59wijxYzz+5gs1m28xW5x+zKvxdLr F5ksbjeuYLOYMH0ti0Xr3iPsFm2rP7A6CHqsmbeG0aOluYfN43JfL5PHzll32T1WLv/C5rFp VSebx79j7B59W1YxenzeJBfAGcVlk5Kak1mWWqRvl8CVsbhpHntBn3zF5znz2BoYZ0h2MXJy SAiYSDy7cZYZwhaTuHBvPVsXIxeHkMAKRomvc7axwRQdv3iHESIxi1Hi+udprBDOF0aJDw8a mUCq2AS0JPa/uAHWISLgLvH13m6wUcwCX5gkWid/B9shLJAtsW92JyuIzSKgKvFr/nOwOK+A q8T/26tZINbJSXzY84gdxOYUcJPY93U62FAhoJrD80HmcAHVNHJInJx9khFikIDEt8mHgJo5 gBKyEpsOQP0jKXFwxQ2WCYzCCxgZVjGKphYkFxQnpRcZ6xUn5haX5qXrJefnbmIERtzpf8/6 dzDePWB9iFGAg1GJhzdjWW6YEGtiWXFl7iFGU6ANE5mlRJPzgXGdVxJvaGxmZGFqYmpsZG5p piTOu1DqZ7CQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxpNccUtiVTZyx6VkOs+YOlsjLXF5 3qpKq93f25sk93xKt/qodWDvzMStxWHLdyhe7tVZOLt+x2NN+2SFwxvaHlVk8edYy+5ue7+t baXckhx3FUmmnEgF0b3WHIYPbdXyLzXHvrkuopS7TNhANOuOc/hdJ/M7yzesOBT/KbVu4uM9 2gbnNmrbKbEUZyQaajEXFScCAO0inkmzAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsVy+t9jQd03yXlhBofULa5/ec5qMf/IOVaL /jcLWS3OvVrJaPH6haFF/+PXzBZnm96wW1zeNYfN4nPvEUaLGef3MVms23iL3eL2ZV6Lpdcv MlncblzBZjFh+loWi9a9R9gt2lZ/YHUQ9Fgzbw2jR0tzD5vH5b5eJo+ds+6ye6xc/oXNY9Oq TjaPf8fYPfq2rGL0+LxJLoAzqoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJ IS8xN9VWycUnQNctMwfoEyWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYQ1j xuKmeewFffIVn+fMY2tgnCHZxcjJISFgInH84h1GCFtM4sK99WxdjFwcQgKzGCWuf57GCuF8 YZT48KCRCaSKTUBLYv+LG2wgtoiAu8TXe7vBOpgFvjBJtE7+zgySEBbIltg3u5MVxGYRUJX4 Nf85WJxXwFXi/+3VLBDr5CQ+7HnEDmJzCrhJ7Ps6HWyoEFDN4fnfmScw8i5gZFjFKJFakFxQ nJSea5SXWq5XnJhbXJqXrpecn7uJERzTz6R3MB7e5X6IUYCDUYmHN3NZbpgQa2JZcWXuIUYJ DmYlEd4Eq7wwId6UxMqq1KL8+KLSnNTiQ4ymQIdNZJYSTc4Hppu8knhDYxMzI0sjc0MLI2Nz JXHefZciw4QE0hNLUrNTUwtSi2D6mDg4pRoY9wT/yZn5pXWDwL7JB+8zvbKX3BMYJL6Fb33N atEb78795rBe/u6as3Rd6IbJ/c+eB32azZ9yTPqktuaE2h9H9yY2nJe4ynGyV+zf87CAD+EN SzdfMFTeL3PjYnTA/BULbV4adLCeTp31aPmDY0rKzcWBV7z/sTZy6k6+fFH8pZi1s/4ZvlTd d0osxRmJhlrMRcWJALWlIKj/AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation for generic exynos bus frequency driver. Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/devfreq/exynos-bus.txt | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt new file mode 100644 index 000000000000..e32daef328da --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -0,0 +1,93 @@ +* Generic Exynos Bus frequency device + +The Samsung Exynos SoC have many buses for data transfer between DRAM +and sub-blocks in SoC. Almost Exynos SoC have the common architecture +for buses. Generally, the each bus of Exynos SoC includes the source clock +and power line and then is able to change the clock according to the usage +of each buses on runtime. When gathering the usage of each buses on runtime, +the driver uses the PPMU (Platform Performance Monitoring Unit) which +is able to measure the current load of sub-blocks. + +There are a little different composition among Exynos SoC because each Exynos +SoC has the different sub-blocks. So, this difference should be specified +in devicetree file instead of each device driver. In result, this driver +is able to support the bus frequency for all Exynos SoCs. + +Required properties for bus device: +- compatible: Should be "samsung,exynos-bus". +- clock-names : the name of clock used by the bus, "bus". +- clocks : phandles for clock specified in "clock-names" property. +- operating-points-v2: the OPP table including frequency/voltage information + to support DVFS (Dynamic Voltage/Frequency Scaling) feature. +- vdd-supply: the regulator to provide the buses with the voltage. +- devfreq-events: the devfreq-event device to monitor the current utilization + of buses. + +Optional properties for bus device: +- exynos,saturation-ratio: the percentage value which is used to calibrate + the performance count against total cycle count. + +Example1: + Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to + power line (regulator). The MIF (Memory Interface) AXI bus is used to + transfer data between DRAM and CPU and uses the VDD_MIF regualtor. + + - power line(VDD_MIF) --> bus for DMC (Dynamic Memory Controller) block + + - MIF bus's frequency/voltage table + ----------------------- + |Lv| Freq | Voltage | + ----------------------- + |L1| 50000 |800000 | + |L2| 100000 |800000 | + |L3| 134000 |800000 | + |L4| 200000 |825000 | + |L5| 400000 |875000 | + ----------------------- + +Example2 : + The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi + is listed below: + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; + + Usage case to handle the frequency and voltage of bus on runtime + in exynos3250-rinato.dts is listed below: + + &bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; /* VDD_MIF */ + status = "okay"; + };