From patchwork Thu Feb 25 08:33:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 8420621 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CB844C0553 for ; Thu, 25 Feb 2016 08:34:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 030CA202E9 for ; Thu, 25 Feb 2016 08:34:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0032F20295 for ; Thu, 25 Feb 2016 08:34:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760140AbcBYIeA (ORCPT ); Thu, 25 Feb 2016 03:34:00 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:40657 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758272AbcBYIce (ORCPT ); Thu, 25 Feb 2016 03:32:34 -0500 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O33004R8H27K700@mailout3.samsung.com>; Thu, 25 Feb 2016 17:32:31 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.133]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 8F.7C.04886.F1CBEC65; Thu, 25 Feb 2016 17:32:31 +0900 (KST) X-AuditID: cbfee690-f79646d000001316-80-56cebc1f0fab Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 51.60.09068.F1CBEC65; Thu, 25 Feb 2016 17:32:31 +0900 (KST) Received: from pankaj.sisodomain.com ([107.108.83.125]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O3300GROH1XWM00@mmp2.samsung.com>; Thu, 25 Feb 2016 17:32:31 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, thomas.ab@samsung.com, olof@lixom.net, p.fedin@samsung.com, Pankaj Dubey , Kukjin Kim Subject: [RESPIN 2/6] drivers: memory: Add support for exynos SROM driver Date: Thu, 25 Feb 2016 14:03:38 +0530 Message-id: <1456389222-12738-3-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1456389222-12738-1-git-send-email-pankaj.dubey@samsung.com> References: <1456389222-12738-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsWyRsSkVVd+z7kwg5lf5SxevzC06F1wlc2i //FrZotNj6+xWlzeNYfNYsb5fUwWp65/ZrN4dWkVm8WirV/YLTqWMTpweWxa1cnmsXlJvceV E02sHn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJVx9coPtoJn7hVtHa9ZGxifWncxcnJICJhI nP1whRXCFpO4cG89WxcjF4eQwApGic9tp4EcDrCio83uEPFZjBLPjn1hhnB+Mkpc//ubCaSb TUBX4sn7ucwgtohAtsT8vd3sIEXMArsYJY59ucYEMklYwFPixuR0kBoWAVWJRdP6wTbzCnhI LP3+lQ3iCjmJk8cmg8U5gcqnnlzMCGILAdXsOdnJBDJTQmAbu8TBxhksEIMEJL5NPsQCcams xKYDzBBzJCUOrrjBMoFReAEjwypG0dSC5ILipPQiE73ixNzi0rx0veT83E2MwPA//e/ZhB2M 9w5YH2IU4GBU4uGN/H02TIg1say4MvcQoynQhonMUqLJ+cAoyyuJNzQ2M7IwNTE1NjK3NFMS 530t9TNYSCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA2O7Qe7cMO7n2bNKZKbMLV4vWr+xsePU rsQJqQGdcad0FzD3NGo0lU9YW9So0ON1l9dB79e+33bcLgc8Vab9O78y2bera+f/nFn779VF npPUEj5os+TQ0rQZcuZPdXwy+jLup9fKGlQzm7HL7HX7KLDH49PP21N9VKbPqv736GOFXqFv yXnxxUosxRmJhlrMRcWJAMVHv3B6AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsVy+t9jQV35PefCDDo/S1q8fmFo0bvgKptF /+PXzBabHl9jtbi8aw6bxYzz+5gsTl3/zGbx6tIqNotFW7+wW3QsY3Tg8ti0qpPNY/OSeo8r J5pYPfq2rGL0+LxJLoA1qoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8x N9VWycUnQNctMwfoJiWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxtUr P9gKnrlXtHW8Zm1gfGrdxcjBISFgInG02b2LkRPIFJO4cG89WxcjF4eQwCxGiWfHvjBDOD8Z Ja7//c0EUsUmoCvx5P1cZhBbRCBbYv7ebnaQImaBXYwSx75cYwKZKizgKXFjcjpIDYuAqsSi af2sIDavgIfE0u9f2SC2yUmcPDYZLM4JVD715GJGEFsIqGbPyU6mCYy8CxgZVjFKpBYkFxQn peca5aWW6xUn5haX5qXrJefnbmIEx9gz6R2Mh3e5H2IU4GBU4uFl+Hk2TIg1say4MvcQowQH s5II7/nF58KEeFMSK6tSi/Lji0pzUosPMZoCHTaRWUo0OR8Y/3kl8YbGJmZGlkZmFkYm5uZK 4ryP/68LExJITyxJzU5NLUgtgulj4uCUamDc9/tLWUjRk/79/0reLFH37mm/ZHvp+jdr0yvf HlUtX8c9Qd5Xf96aj+WbF/gFb2V9f/A5s1/3NwOPjyUbaoOrbuQYbN3x4uG78q2FpkcdRFW5 H1swdsWGBUwTmnBPJ0zF6GtSpJHXn/SXzuaTXDmv+6p+3he4S2Eto9ERRdX9C9SeNNuXi0Ur sRRnJBpqMRcVJwIAnYyuEccCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Exynos SROM controller driver which will handle save restore of SROM registers during S2R. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski [p.fedin@samsung.com: tested on SMDK5410] Tested-by: Pavel Fedin Signed-off-by: Kukjin Kim Signed-off-by: Krzysztof Kozlowski --- drivers/memory/Kconfig | 1 + drivers/memory/Makefile | 1 + drivers/memory/samsung/Kconfig | 12 +++ drivers/memory/samsung/Makefile | 1 + drivers/memory/samsung/exynos-srom.c | 175 +++++++++++++++++++++++++++++++++++ drivers/memory/samsung/exynos-srom.h | 51 ++++++++++ 6 files changed, 241 insertions(+) create mode 100644 drivers/memory/samsung/Kconfig create mode 100644 drivers/memory/samsung/Makefile create mode 100644 drivers/memory/samsung/exynos-srom.c create mode 100644 drivers/memory/samsung/exynos-srom.h diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 6f31546..bcb1982 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -114,6 +114,7 @@ config JZ4780_NEMC the Ingenic JZ4780. This controller is used to handle external memory devices such as NAND and SRAM. +source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" endif diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 1c46af5..d100e40 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -16,4 +16,5 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o +obj-$(CONFIG_SAMSUNG_MC) += samsung/ obj-$(CONFIG_TEGRA_MC) += tegra/ diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig new file mode 100644 index 0000000..c2cd45e --- /dev/null +++ b/drivers/memory/samsung/Kconfig @@ -0,0 +1,12 @@ +config SAMSUNG_MC + bool "SAMSUNG Exynos Memory Controller support" if COMPILE_TEST + default y + depends on ARCH_EXYNOS + help + This driver supports the Memory Controller (MC) hardwares found on + SAMSUNG Exynos SoCs. + +config EXYNOS_SROM + bool + depends on (ARM && ARCH_EXYNOS && PM) || ((ARM || ARM64) && COMPILE_TEST) + diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile new file mode 100644 index 0000000..9c554d5 --- /dev/null +++ b/drivers/memory/samsung/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/memory/samsung/exynos-srom.c b/drivers/memory/samsung/exynos-srom.c new file mode 100644 index 0000000..57a232d --- /dev/null +++ b/drivers/memory/samsung/exynos-srom.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - SROM Controller support + * Author: Pankaj Dubey + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "exynos-srom.h" + +static const unsigned long exynos_srom_offsets[] = { + /* SROM side */ + EXYNOS_SROM_BW, + EXYNOS_SROM_BC0, + EXYNOS_SROM_BC1, + EXYNOS_SROM_BC2, + EXYNOS_SROM_BC3, +}; + +/** + * struct exynos_srom_reg_dump: register dump of SROM Controller registers. + * @offset: srom register offset from the controller base address. + * @value: the value of register under the offset. + */ +struct exynos_srom_reg_dump { + u32 offset; + u32 value; +}; + +/** + * struct exynos_srom: platform data for exynos srom controller driver. + * @dev: platform device pointer + * @reg_base: srom base address + * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value. + */ +struct exynos_srom { + struct device *dev; + void __iomem *reg_base; + struct exynos_srom_reg_dump *reg_offset; +}; + +static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump( + const unsigned long *rdump, + unsigned long nr_rdump) +{ + struct exynos_srom_reg_dump *rd; + unsigned int i; + + rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL); + if (!rd) + return NULL; + + for (i = 0; i < nr_rdump; ++i) + rd[i].offset = rdump[i]; + + return rd; +} + +static int exynos_srom_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct exynos_srom *srom; + struct device *dev = &pdev->dev; + + np = dev->of_node; + if (!np) { + dev_err(&pdev->dev, "could not find device info\n"); + return -EINVAL; + } + + srom = devm_kzalloc(&pdev->dev, + sizeof(struct exynos_srom), GFP_KERNEL); + if (!srom) + return -ENOMEM; + + srom->dev = dev; + srom->reg_base = of_iomap(np, 0); + if (!srom->reg_base) { + dev_err(&pdev->dev, "iomap of exynos srom controller failed\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, srom); + + srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets, + sizeof(exynos_srom_offsets)); + if (!srom->reg_offset) { + iounmap(srom->reg_base); + return -ENOMEM; + } + + return 0; +} + +static int exynos_srom_remove(struct platform_device *pdev) +{ + struct exynos_srom *srom = platform_get_drvdata(pdev); + + kfree(srom->reg_offset); + iounmap(srom->reg_base); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static void exynos_srom_save(void __iomem *base, + struct exynos_srom_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + rd->value = readl(base + rd->offset); +} + +static void exynos_srom_restore(void __iomem *base, + const struct exynos_srom_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + writel(rd->value, base + rd->offset); +} + +static int exynos_srom_suspend(struct device *dev) +{ + struct exynos_srom *srom = dev_get_drvdata(dev); + + exynos_srom_save(srom->reg_base, srom->reg_offset, + ARRAY_SIZE(exynos_srom_offsets)); + return 0; +} + +static int exynos_srom_resume(struct device *dev) +{ + struct exynos_srom *srom = dev_get_drvdata(dev); + + exynos_srom_restore(srom->reg_base, srom->reg_offset, + ARRAY_SIZE(exynos_srom_offsets)); + return 0; +} +#endif + +static const struct of_device_id of_exynos_srom_ids[] = { + { + .compatible = "samsung,exynos-srom", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_exynos_srom_ids); + +static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume); + +static struct platform_driver exynos_srom_driver = { + .probe = exynos_srom_probe, + .remove = exynos_srom_remove, + .driver = { + .name = "exynos-srom", + .of_match_table = of_exynos_srom_ids, + .pm = &exynos_srom_pm_ops, + }, +}; +module_platform_driver(exynos_srom_driver); + +MODULE_AUTHOR("Pankaj Dubey "); +MODULE_DESCRIPTION("Exynos SROM Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/memory/samsung/exynos-srom.h b/drivers/memory/samsung/exynos-srom.h new file mode 100644 index 0000000..34660c6 --- /dev/null +++ b/drivers/memory/samsung/exynos-srom.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Exynos SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __EXYNOS_SROM_H +#define __EXYNOS_SROM_H __FILE__ + +#define EXYNOS_SROMREG(x) (x) + +#define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0) +#define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4) +#define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8) +#define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc) +#define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10) +#define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14) +#define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0 +#define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1 +#define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2 +#define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3 + +#define EXYNOS_SROM_BW__CS_MASK 0xf + +#define EXYNOS_SROM_BW__NCS0__SHIFT 0 +#define EXYNOS_SROM_BW__NCS1__SHIFT 4 +#define EXYNOS_SROM_BW__NCS2__SHIFT 8 +#define EXYNOS_SROM_BW__NCS3__SHIFT 12 +#define EXYNOS_SROM_BW__NCS4__SHIFT 16 +#define EXYNOS_SROM_BW__NCS5__SHIFT 20 + +/* applies to same to BCS0 - BCS3 */ + +#define EXYNOS_SROM_BCX__PMC__SHIFT 0 +#define EXYNOS_SROM_BCX__TACP__SHIFT 4 +#define EXYNOS_SROM_BCX__TCAH__SHIFT 8 +#define EXYNOS_SROM_BCX__TCOH__SHIFT 12 +#define EXYNOS_SROM_BCX__TACC__SHIFT 16 +#define EXYNOS_SROM_BCX__TCOS__SHIFT 24 +#define EXYNOS_SROM_BCX__TACS__SHIFT 28 + +#endif /* __EXYNOS_SROM_H */