From patchwork Tue Mar 15 02:08:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8584821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 47B969F54C for ; Tue, 15 Mar 2016 02:09:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 643CA20375 for ; Tue, 15 Mar 2016 02:09:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 580B720306 for ; Tue, 15 Mar 2016 02:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933630AbcCOCI0 (ORCPT ); Mon, 14 Mar 2016 22:08:26 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:44629 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752386AbcCOCIU (ORCPT ); Mon, 14 Mar 2016 22:08:20 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4201O9U5XTFU30@mailout2.samsung.com>; Tue, 15 Mar 2016 11:08:17 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.115]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 8B.E3.04964.19E67E65; Tue, 15 Mar 2016 11:08:17 +0900 (KST) X-AuditID: cbfee68f-f793a6d000001364-95-56e76e916062 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 0B.88.09068.19E67E65; Tue, 15 Mar 2016 11:08:17 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4200KQD5XS3G60@mmp2.samsung.com>; Tue, 15 Mar 2016 11:08:16 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/7] clk: samsung: exynos3250: Add UART2 clock Date: Tue, 15 Mar 2016 11:08:09 +0900 Message-id: <1458007695-3627-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458007695-3627-1-git-send-email-cw00.choi@samsung.com> References: <1458007695-3627-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsWyRsSkWHdi3vMwgy13RS22H3nGanH9y3NW i/lHzrFaTLo/gcXixq82VovXLwwt+h+/ZrbY9Pgaq8XlXXPYLGac38dksWjrF3aLw2/aWS1m TH7JZrFq1x9GBz6PnbPusntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZUy7 8ZKxYLtMxZLLR1gbGG+LdzFyckgImEh0bVjKCmGLSVy4t56ti5GLQ0hgBaPEy8Ov2WGKJk54 xwyRmMUo0XGuDSwhJPCFUeLIyzoQm01AS2L/ixtsILaIQJzExIsQNrPALCaJefMLQWxhAUeJ w1NamUBsFgFViU2bNjOD2LwCLhIdsz8xQSyTk/iw5xHYfE4BV4kVNz6yQOxykVi0og3sOgmB c+wSc6/8ZIcYJCDxbfIhoCIOoISsxKYDzBBzJCUOrrjBMoFReAEjwypG0dSC5ILipPQiY73i xNzi0rx0veT83E2MwEg5/e9Z/w7GuwesDzEKcDAq8fDOkHoeJsSaWFZcmXuI0RRow0RmKdHk fGA85pXEGxqbGVmYmpgaG5lbmimJ8y6U+hksJJCeWJKanZpakFoUX1Sak1p8iJGJg1OqgbFj 3597kqmBL4Q3RnFwL/eUj/EucM2pmB4ns+e3zIT52lw6/357Hsp5d91mttKmdztMJf5UBdya eHLDqlnRpTv0d959n/Bp3n5lv4n1zo/rVL6/vSl44mrEks+Rse5CrwoXr62ysQv1YJ1WkmGe lpKYm7TL+p3CA/WGvs2Pd2/8Je56v0pr7gclluKMREMt5qLiRAAZSTEnjwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJIsWRmVeSWpSXmKPExsVy+t9jQd2Jec/DDNa0ClhsP/KM1eL6l+es FvOPnGO1mHR/AovFjV9trBavXxha9D9+zWyx6fE1VovLu+awWcw4v4/JYtHWL+wWh9+0s1rM mPySzWLVrj+MDnweO2fdZffYtKqTzWPzknqPvi2rGD0+b5ILYI1qYLTJSE1MSS1SSM1Lzk/J zEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQdcvMATpUSaEsMacUKBSQWFyspG+HaUJo iJuuBUxjhK5vSBBcj5EBGkhYw5gx7cZLxoLtMhVLLh9hbWC8Ld7FyMkhIWAiMXHCO2YIW0zi wr31bF2MXBxCArMYJTrOtbGDJIQEvjBKHHlZB2KzCWhJ7H9xgw3EFhGIk5h4EcJmFpjFJDFv fiGILSzgKHF4SisTiM0ioCqxadNmsAW8Ai4SHbM/MUEsk5P4sOcR2HxOAVeJFTc+skDscpFY tKKNbQIj7wJGhlWMEqkFyQXFSem5Rnmp5XrFibnFpXnpesn5uZsYwdH4THoH4+Fd7ocYBTgY lXh4Z0g9DxNiTSwrrsw9xCjBwawkwpuQABTiTUmsrEotyo8vKs1JLT7EaAp02ERmKdHkfGCi yCuJNzQ2MTOyNDI3tDAyNlcS5338f12YkEB6YklqdmpqQWoRTB8TB6dUAyM7U8e3mYX/OF5e OuXUuI8h2+PJ/o8X+Gon/kyOcmGJKsxzzZskIlkv2Bsl326VsPz73U/Ra5pNt5ydcW660Nsf 08L5Lb7W8HWobGVtbtW6Nvv+LJPXEXc/GO9VW1Qnv3/aoTathGse7L41zF82xTFfuB0UIOR6 v/DgSw3x+fw7rLwFdA88vqPEUpyRaKjFXFScCAD8Ky4T3AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Pankaj Dubey Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos3250.c | 6 ++++++ include/dt-bindings/clock/exynos3250.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index fdd41b17a24f..bc60e399d1bc 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), /* DIV_PERIL0 */ + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), }; diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..ddb874130d86 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,7 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +128,7 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +225,7 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +252,13 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 249 /* * CMU DMC