From patchwork Thu Mar 24 04:25:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8657141 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E2761C0553 for ; Thu, 24 Mar 2016 04:27:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E88C020375 for ; Thu, 24 Mar 2016 04:27:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D986020379 for ; Thu, 24 Mar 2016 04:27:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751422AbcCXE1O (ORCPT ); Thu, 24 Mar 2016 00:27:14 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:60862 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932284AbcCXEZt (ORCPT ); Thu, 24 Mar 2016 00:25:49 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4J01E6I0AM8000@mailout3.samsung.com>; Thu, 24 Mar 2016 13:25:34 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.115]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id C1.CD.04949.E3C63F65; Thu, 24 Mar 2016 13:25:34 +0900 (KST) X-AuditID: cbfee68d-f79646d000001355-4c-56f36c3efd64 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id E3.11.13906.E3C63F65; Thu, 24 Mar 2016 13:25:34 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4J007XC0AJOI80@mmp1.samsung.com>; Thu, 24 Mar 2016 13:25:34 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, tjakobi@math.uni-bielefeld.de, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v5 14/21] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Thu, 24 Mar 2016 13:25:23 +0900 Message-id: <1458793530-31897-15-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> References: <1458793530-31897-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIIsWRmVeSWpSXmKPExsWyRsSkWNcu53OYwZVVBhbXvzxntZh/5Byr Rf+bhawW516tZLR4/cLQov/xa2aLs01v2C02Pb7GanF51xw2i8+9RxgtZpzfx2SxbuMtdovb l3ktll6/yGRxu3EFm8WE6WtZLM6cvsRq0br3CLtF2+oPrA7CHmvmrWH0aGnuYfO43NfL5LFz 1l12j5XLv7B5bFrVyeaxeUm9x79j7B5brrazePRtWcXo8XmTXAB3FJdNSmpOZllqkb5dAlfG 9PZzrAVrlSumP/rF2sD4TaqLkYNDQsBE4sSp2C5GTiBTTOLCvfVsXYxcHEICKxglJm5ZzgKR MJHYMm8bI0RiKaPEoZO3mUESQgJfGCUm/AErYhPQktj/4gYbiC0ikCLx+OFJsEnMAlOYJZZP bwYrEhbwk+icspEJxGYRUJV4v7SJFcTmFXCTeLjpNxPENjmJD3sesYPYnEDxqQ1NLBDLXCWe Pt7ECjJUQmAuh0Tv21lQgwQkvk0+xALxjqzEpgPMEHMkJQ6uuMEygVF4ASPDKkbR1ILkguKk 9CJDveLE3OLSvHS95PzcTYzAmDz971nvDsbbB6wPMQpwMCrx8DZwfA4TYk0sK67MPcRoCrRh IrOUaHI+MPLzSuINjc2MLExNTI2NzC3NlMR5FaV+BgsJpCeWpGanphakFsUXleakFh9iZOLg lGpgrF5XPN9p94LZ4hs/+b5+zf2O78PN63t/qf075ngxrSTiQHBa+TEj531nbqvMOPUh6GhN reERI9vfh/4yn9aWaVglefcC/8xTS220brcf/dxwMT5/29GU3xKfC7ZynGx6Hsv5WC532SZO xnvMk12+h4mFLC/0zPgwZ3GlhcvturD817NyNh2d6aDEUpyRaKjFXFScCAA+oUEyxAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPIsWRmVeSWpSXmKPExsVy+t9jAV27nM9hBk9eqllc//Kc1WL+kXOs Fv1vFrJanHu1ktHi9QtDi/7Hr5ktzja9YbfY9Pgaq8XlXXPYLD73HmG0mHF+H5PFuo232C1u X+a1WHr9IpPF7cYVbBYTpq9lsThz+hKrReveI+wWbas/sDoIe6yZt4bRo6W5h83jcl8vk8fO WXfZPVYu/8LmsWlVJ5vH5iX1Hv+OsXtsudrO4tG3ZRWjx+dNcgHcUQ2MNhmpiSmpRQqpecn5 KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlA3ykplCXmlAKFAhKLi5X07TBN CA1x07WAaYzQ9Q0JgusxMkADCWsYM6a3n2MtWKtcMf3RL9YGxm9SXYycHBICJhJb5m1jhLDF JC7cW8/WxcjFISSwlFHi0MnbzCAJIYEvjBIT/rCA2GwCWhL7X9xgA7FFBFIkHj88CdbALDCF WWL59GawImEBP4nOKRuZQGwWAVWJ90ubWEFsXgE3iYebfjNBbJOT+LDnETuIzQkUn9rQxAKx zFXi6eNNrBMYeRcwMqxilEgtSC4oTkrPNcxLLdcrTswtLs1L10vOz93ECI78Z1I7GA/ucj/E KMDBqMTDe4Prc5gQa2JZcWXuIUYJDmYlEd714UAh3pTEyqrUovz4otKc1OJDjKZAh01klhJN zgcmpbySeENjEzMjSyNzQwsjY3Mlcd7H/9eFCQmkJ5akZqemFqQWwfQxcXBKNTAuFZEx3sUT V/Ftqv6uZ3U+LiUrp3yaVsQY8E0uo9DCY7K/6Iwli7x/mWpymD371fXhXspcLaf86BYL1TtH tz14cWxew9lDfOypE93sFaxeMsQvKFi+5diMxm9rJS9aLsxR/XzbRX8x72zfWXITir5sdq7V ff3IcndAx4eC1hnsWhcieVmt70crsRRnJBpqMRcVJwIASrO+DhIDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 1ae72c4fa55e..b5157492a422 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -722,6 +722,153 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; };