From patchwork Sun Mar 27 23:38:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8676971 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 083F89F65E for ; Sun, 27 Mar 2016 23:41:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 261712021B for ; Sun, 27 Mar 2016 23:41:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BCC220253 for ; Sun, 27 Mar 2016 23:41:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753772AbcC0Xk5 (ORCPT ); Sun, 27 Mar 2016 19:40:57 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:57104 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753486AbcC0Xi3 (ORCPT ); Sun, 27 Mar 2016 19:38:29 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4Q02SSQ1NSN3A0@mailout3.samsung.com>; Mon, 28 Mar 2016 08:38:16 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.113]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 62.45.04804.7EE68F65; Mon, 28 Mar 2016 08:38:16 +0900 (KST) X-AuditID: cbfee690-f79e56d0000012c4-c5-56f86ee7d720 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 06.82.06682.7EE68F65; Mon, 28 Mar 2016 08:38:15 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4Q0044Y1NPUV30@mmp1.samsung.com>; Mon, 28 Mar 2016 08:38:15 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v6 14/21] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 Date: Mon, 28 Mar 2016 08:38:03 +0900 Message-id: <1459121890-4601-15-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459121890-4601-1-git-send-email-cw00.choi@samsung.com> References: <1459121890-4601-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsWyRsSkUPdF3o8wg10VFte/PGe1mH/kHKtF /5uFrBbnXq1ktJh0fwKLxesXhhb9j18zW5xtesNusenxNVaLy7vmsFl87j3CaDHj/D4mi3Ub b7Fb3L7Ma/HyyA9Gi6XXLzJZ3G5cwWYxYfpaFoszpy+xWrTuPcJu0bb6A6uDqMeaeWsYPVqa e9g8Lvf1MnnculPvsXPWXXaPlcu/sHlsWtXJ5rF5Sb3Hv2PsHluutrN49G1ZxejxeZNcAE8U l01Kak5mWWqRvl0CV8b09nOsBWuVK6Y/+sXawPhNqouRk0NCwETiz/mzLBC2mMSFe+vZuhi5 OIQEVjBKnHh6mQ2m6PWm0+wQiaWMEl3T77BCOF8YJZ4/O8QIUsUmoCWx/8UNsA4RgRSJxw9P go1iFjjCLDF14w0mkISwgJ/ElzXTWEFsFgFVibZN55hBbF4BV4m7L46wQqyTk/iw5xE7iM0J FG/+OhdsgZCAi8S2l8vAzpAQ2MIh8WL7F2aIQQIS3yYfAnqCAyghK7HpADPEHEmJgytusExg FF7AyLCKUTS1ILmgOCm9yESvODG3uDQvXS85P3cTIzBiT/97NmEH470D1ocYBTgYlXh4Myx/ hAmxJpYVV+YeYjQF2jCRWUo0OR+YFvJK4g2NzYwsTE1MjY3MLc2UxHlfS/0MFhJITyxJzU5N LUgtii8qzUktPsTIxMEp1cAoIGs+43VRqoLTof3OAazOx+ycZnj/DjxvXNVQ4ukYE+X1e9/D muucIZe+bw5inSR8p/rXm+s9YUkawv0FJQlGGmVOhR0bP/zZ1Vnw0r69/4q67amrJ8T+H9FZ w8G808tBc4YsR3nTO99/Zs9tpnK9LWPuvmE9PzhNh3uXx4U3yqpZOzySNyuxFGckGmoxFxUn AgBJSGlY0wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjleLIzCtJLcpLzFFi42I5/e+xgO7zvB9hBgd6zC2uf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3aJt9QdWB1GPNfPWMHq0 NPeweVzu62XyuHWn3mPnrLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQCe qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygX5UU yhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGdPbz7EWrFWumP7oF2sD4zep LkZODgkBE4nXm06zQ9hiEhfurWfrYuTiEBJYyijRNf0OK4TzhVHi+bNDjCBVbAJaEvtf3GAD sUUEUiQePzwJ1sEscIRZYurGG0wgCWEBP4kva6axgtgsAqoSbZvOMYPYvAKuEndfHGGFWCcn 8WHPI7DVnEDx5q9zwRYICbhIbHu5jH0CI+8CRoZVjBKpBckFxUnpuYZ5qeV6xYm5xaV56XrJ +bmbGMFp4ZnUDsaDu9wPMQpwMCrx8GZY/ggTYk0sK67MPcQowcGsJMJblQYU4k1JrKxKLcqP LyrNSS0+xGgKdNhEZinR5HxgysoriTc0NjEzsjQyN7QwMjZXEud9/H9dmJBAemJJanZqakFq EUwfEwenVANj5vqWJxXHCna8TNDnPKWf0rD87d9Xd7cuevh7HueVx92tvIE/Qi+//Vxju5/3 86I9CZPvvIr4My+SqUlXrfhe2tarTZ92O0R4vdCv2b5/f3F/x4X3Trd7eKdVvdOIEp+q1rFm 1wep090H5YrOf2Z661VieW2di0bt66uSG2RZEisvtzf8ESmWVGIpzkg01GIuKk4EADAY4Qgh AwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 1ae72c4fa55e..b5157492a422 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -722,6 +722,153 @@ opp-microvolt = <875000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + + bus_isp_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + + bus_peril_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; };