From patchwork Sun Mar 27 23:38:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8676851 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 156BCC0553 for ; Sun, 27 Mar 2016 23:40:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 284512021F for ; Sun, 27 Mar 2016 23:40:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2330F20218 for ; Sun, 27 Mar 2016 23:40:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754071AbcC0Xk1 (ORCPT ); Sun, 27 Mar 2016 19:40:27 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:57104 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752441AbcC0Xib (ORCPT ); Sun, 27 Mar 2016 19:38:31 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4Q034KO1NS3C90@mailout3.samsung.com>; Mon, 28 Mar 2016 08:38:16 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.113]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D3.45.04804.8EE68F65; Mon, 28 Mar 2016 08:38:16 +0900 (KST) X-AuditID: cbfee690-f79e56d0000012c4-cb-56f86ee84343 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 67.82.06682.7EE68F65; Mon, 28 Mar 2016 08:38:16 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4Q0044Y1NPUV30@mmp1.samsung.com>; Mon, 28 Mar 2016 08:38:15 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v6 16/21] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Mon, 28 Mar 2016 08:38:05 +0900 Message-id: <1459121890-4601-17-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459121890-4601-1-git-send-email-cw00.choi@samsung.com> References: <1459121890-4601-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsWyRsSkUPdF3o8wg0VH+C2uf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3aJt9QdWB1GPNfPWMHq0 NPeweVzu62XyuHWn3mPnrLvsHiuXf2Hz2LSqk81j85J6j3/H2D22XG1n8ejbsorR4/MmuQCe KC6blNSczLLUIn27BK6MO29Psxd8kqno2X2BrYGxQ7yLkYNDQsBE4vGOnC5GTiBTTOLCvfVs XYxcHEICKxglbp+7zgiRMJE4su01E0RiKaPEonXnoZwvjBLPnx0Cq2IT0JLY/+IGG4gtIpAi 8fjhSbBRzAJHmCWmbrzBBJIQFvCTOPjrBFgRi4CqxP45TWA2r4CrxPL2dawQ6+QkPux5xA5i cwLFm7/OBVsgJOAise3lMnaQoRICazkkZnzYDTVIQOLb5EMsEP/ISmw6wAwxR1Li4IobLBMY hRcwMqxiFE0tSC4oTkovMtErTswtLs1L10vOz93ECIzY0/+eTdjBeO+A9SFGAQ5GJR7eDMsf YUKsiWXFlbmHGE2BNkxklhJNzgemhbySeENjMyMLUxNTYyNzSzMlcd7XUj+DhQTSE0tSs1NT C1KL4otKc1KLDzEycXBKNTDWp5v+8kll/3Hp88mjs/vyZTZU/f9fGP40PFFoc9X3tvw3p9+G OuZ+mDOPb/3DHdMf6cxrkCj4tFX56IWvqi8sSxWanm3kD17NIOf/f+bPrIIZXDMMa+JjxfaV 90xQOXjkxzuLV8JHEtULY3S3iTU3bRT1zgy6u2JB2/c98+NOC9SJPnu1tXGjEktxRqKhFnNR cSIA0jkpmNMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjleLIzCtJLcpLzFFi42I5/e+xgO6LvB9hBtvuclhc//Kc1WL+kXOs Fv1vFrJanHu1ktFi0v0JLBavXxha9D9+zWxxtukNu8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCzW bbzFbnH7Mq/FyyM/GC2WXr/IZHG7cQWbxYTpa1kszpy+xGrRuvcIu0Xb6g+sDqIea+atYfRo ae5h87jc18vkcetOvcfOWXfZPVYu/8LmsWlVJ5vH5iX1Hv+OsXtsudrO4tG3ZRWjx+dNcgE8 UQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAvyop lCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM+68Pc1e8Emmomf3BbYGxg7x LkZODgkBE4kj214zQdhiEhfurWfrYuTiEBJYyiixaN15JgjnC6PE82eHGEGq2AS0JPa/uMEG YosIpEg8fngSrINZ4AizxNSNN8BGCQv4SRz8dQKsiEVAVWL/nCYwm1fAVWJ5+zpWiHVyEh/2 PGIHsTmB4s1f54ItEBJwkdj2chn7BEbeBYwMqxglUguSC4qT0nMN81LL9YoTc4tL89L1kvNz NzGC08IzqR2MB3e5H2IU4GBU4uHNsPwRJsSaWFZcmXuIUYKDWUmEtyoNKMSbklhZlVqUH19U mpNafIjRFOiwicxSosn5wJSVVxJvaGxiZmRpZG5oYWRsriTO+/j/ujAhgfTEktTs1NSC1CKY PiYOTqkGRvsy8fJLkzKTnmgH63XOsHGO+ru665DCCf5Tsi1/xZ5zJd82fyu9NvzsR9biymvP c/S87vq+WSd1vKbx+YfI1hk39qgVG3cb6U8S+vbUcfkL1uS4jSpN+hcOra43k1u9tV16rvyc 7oA8+/+2XysT71zz4kj6M7lM8W141qMATg7m8xkT3ZbLKrEUZyQaajEXFScCAMge1V0hAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl Tested-by: Anand Moon --- arch/arm/boot/dts/exynos4x12.dtsi | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 99a0f4ca3d47..e5173107ed44 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -349,6 +349,112 @@ opp-hz = /bits/ 64 <267000000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; &combiner {