From patchwork Thu Mar 31 02:47:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8707031 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 695D0C0553 for ; Thu, 31 Mar 2016 02:48:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8E6742020F for ; Thu, 31 Mar 2016 02:48:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0F59320386 for ; Thu, 31 Mar 2016 02:48:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755644AbcCaCsW (ORCPT ); Wed, 30 Mar 2016 22:48:22 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:52227 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752151AbcCaCsS (ORCPT ); Wed, 30 Mar 2016 22:48:18 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4V02RVUUGAAB60@mailout1.samsung.com>; Thu, 31 Mar 2016 11:48:10 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.112]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id E1.AB.04785.AEF8CF65; Thu, 31 Mar 2016 11:48:10 +0900 (KST) X-AuditID: cbfee68e-f79d96d0000012b1-99-56fc8fea8c51 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 4D.9A.06699.AEF8CF65; Thu, 31 Mar 2016 11:48:10 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O4V00BJVUG94S30@mmp2.samsung.com>; Thu, 31 Mar 2016 11:48:09 +0900 (KST) From: Chanwoo Choi To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 3/9] clk: samsung: exynos3250: Add UART2 clock Date: Thu, 31 Mar 2016 11:47:59 +0900 Message-id: <1459392485-11327-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> References: <1459392485-11327-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWyRsSkQPdV/58wg79XRC22H3nGanH9y3NW i/lHzrFaTLo/gcXixq82VovXLwwt+h+/ZrbY9Pgaq8XlXXPYLGac38dksWjrF3aLw2/aWS1m TH7JZrFq1x9GBz6PnbPusntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZSxp XMlUcEaoontmD2sD43f+LkZODgkBE4lTl5cwQ9hiEhfurWfrYuTiEBJYwSjxcvYqdpiiGRc2 soLYQgKzGCX+/3eCsL8wSnTe8gSx2QS0JPa/uMEGYosIxElMvAhhMwvMYpKYN78QxBYWcJS4 8eosUxcjBweLgKrEr2ZXEJNXwFVi0rwgiE1yEh/2PALbyingJnFvxWV2iE2uEmtmzmEGOU1C 4Bi7xKv5V5lAEiwCAhLfJh9iAZkjISArsekA1CuSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGR XnFibnFpXrpecn7uJkZgjJz+96xvB+PNA9aHGAU4GJV4eDXS/oQJsSaWFVfmHmI0BdowkVlK NDkfGIl5JfGGxmZGFqYmpsZG5pZmSuK8CVI/g4UE0hNLUrNTUwtSi+KLSnNSiw8xMnFwSjUw Lu59Wan12OHxio/zPAPuvxVsWd9W/6Am+br2vgOcvMudD6RcuSvocsU10Oe6+fRf+3+qS69f WBF5bXeb0ryLuWe2192LkYi9xlIUmOccd/dPdTgH3yPJotqde65sLam5tVjwq8WtVXVrIlMV E7yPL1r/ouZ5hJbBqs+Prly5Ovm63qYyA5Gq60osxRmJhlrMRcWJANjU22uMAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t9jQd1X/X/CDH5v5rfYfuQZq8X1L89Z LeYfOcdqMen+BBaLG7/aWC1evzC06H/8mtli0+NrrBaXd81hs5hxfh+TxaKtX9gtDr9pZ7WY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8fmJfUefVtWMXp83iQXwBrVwGiTkZqYklqkkJqXnJ+S mZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SokkJZYk4pUCggsbhYSd8O04TQ EDddC5jGCF3fkCC4HiMDNJCwhjFjSeNKpoIzQhXdM3tYGxi/83cxcnJICJhIzLiwkRXCFpO4 cG89G4gtJDCLUeL/fycI+wujROctTxCbTUBLYv+LG2A1IgJxEhMvQtjMArOYJObNLwSxhQUc JW68OsvUxcjBwSKgKvGr2RXE5BVwlZg0Lwhik5zEhz2P2EFsTgE3iXsrLrNDbHKVWDNzDvME Rt4FjAyrGCVSC5ILipPSc43yUsv1ihNzi0vz0vWS83M3MYLj8Jn0DsbDu9wPMQpwMCrx8F5I /hMmxJpYVlyZe4hRgoNZSYQ3tA8oxJuSWFmVWpQfX1Sak1p8iNEU6KyJzFKiyfnAFJFXEm9o bGJmZGlkbmhhZGyuJM77+P+6MCGB9MSS1OzU1ILUIpg+Jg5OqQZGpcOXjV7OW//9oW9JT/7p 5Te3PQg7v3zJDE+HfcsDPU0npU8MdDQWvGV/k325RPkqx8n/rAXmX5iR5hueLeZTrFFbM59N blbxgpZa/cNCPyfNf1/1/Ps9b/Orav+/7pc7vWZz4dka71n/Ngje2tIxz2oDj351hLymjSJb 8xYxTUH7jF1iLxNZlViKMxINtZiLihMB2WbHLNkCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Pankaj Dubey Signed-off-by: Chanwoo Choi --- drivers/clk/samsung/clk-exynos3250.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index fdd41b17a24f..bc60e399d1bc 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = { DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), /* DIV_PERIL0 */ + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), };