From patchwork Mon Apr 11 03:57:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8796361 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6E9599F54F for ; Mon, 11 Apr 2016 03:59:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8A4CC20204 for ; Mon, 11 Apr 2016 03:59:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8459E20260 for ; Mon, 11 Apr 2016 03:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752409AbcDKD63 (ORCPT ); Sun, 10 Apr 2016 23:58:29 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:40232 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752387AbcDKD60 (ORCPT ); Sun, 10 Apr 2016 23:58:26 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5G01NABB0Q5KD0@mailout4.samsung.com>; Mon, 11 Apr 2016 12:58:02 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.115]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 3F.23.04789.AC02B075; Mon, 11 Apr 2016 12:58:02 +0900 (KST) X-AuditID: cbfee691-f795a6d0000012b5-3a-570b20ca9673 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 9C.29.06699.9C02B075; Mon, 11 Apr 2016 12:58:02 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O5G00DWZB0M9H20@mmp2.samsung.com>; Mon, 11 Apr 2016 12:58:01 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v9 15/20] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 Date: Mon, 11 Apr 2016 12:57:53 +0900 Message-id: <1460347078-15175-16-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> References: <1460347078-15175-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsWyRsSkWPeUAne4QfsBXovrX56zWsw/co7V ov/NQlaLc69WMlpMuj+BxeL1C0OL/sevmS3ONr1ht9j0+BqrxeVdc9gsPvceYbSYcX4fk8W6 jbfYLW5f5rV4eeQHo8XS6xeZLG43rmCzmDB9LYvFmdOXWC1a9x5htzj8pp3Vom31B1aLVbv+ MDqIe6yZt4bRo6W5h83jcl8vk8etO/UeO2fdZfdYufwLm8emVZ1sHpuX1Hv8O8buseVqO4tH 35ZVjB6fN8kF8ERx2aSk5mSWpRbp2yVwZdx5e5q94JNMRc/uC2wNjB3iXYycHBICJhJLdp1g hrDFJC7cW8/WxcjFISSwglHi0fTN7DBFDxe/ZQOxhQRmMUp8ORQAYX9hlOj8lgRiswloSex/ cQOsWURgKqPE51NtLCAOs8ARZompG28wgVQJC/hJLJ5zHmgqBweLgKrEuyYOkDCvgJvEotaX UFfISXzY8whsMSdQ/NP6dlaQciEBV4lnn+tARkoIHOGQeP34AwtIDYuAgMS3yYdYQGokBGQl Nh2AGiMpcXDFDZYJjMILGBlWMYqmFiQXFCelF5nqFSfmFpfmpesl5+duYgRG8Ol/zybuYLx/ wPoQowAHoxIPr8M1rnAh1sSy4srcQ4ymQBsmMkuJJucD00ReSbyhsZmRhamJqbGRuaWZkjiv jvTPYCGB9MSS1OzU1ILUovii0pzU4kOMTBycUg2MGm6/r23/dGvp1FKjq+FnukPmtrxvOcZ4 82jXpRr2vfnBxXoLiy494RCS1zrPGb7VwCAuiqNN9eOnQ6vVVQtOrpJd19rtt2nzrK0PTOWj 41Pc5ydJy7Al2Uauj572WTXJ2/pe870NWZ9jJsYuUuuc7pilMWUfi/Xbv89N9y7V7oy5cOn5 Jas9SizFGYmGWsxFxYkA38DXY9sCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsVy+t9jQd1TCtzhBk8/s1lc//Kc1WL+kXOs Fv1vFrJanHu1ktFi0v0JLBavXxha9D9+zWxxtukNu8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCzW bbzFbnH7Mq/FyyM/GC2WXr/IZHG7cQWbxYTpa1kszpy+xGrRuvcIu8XhN+2sFm2rP7BarNr1 h9FB3GPNvDWMHi3NPWwel/t6mTxu3an32DnrLrvHyuVf2Dw2repk89i8pN7j3zF2jy1X21k8 +rasYvT4vEkugCeqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJ xSdA1y0zB+hrJYWyxJxSoFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhDWPGnben2Qs+ yVT07L7A1sDYId7FyMkhIWAi8XDxWzYIW0ziwr31YLaQwCxGiS+HAiDsL4wSnd+SQGw2AS2J /S9uANVwcYgITGWU+HyqjQXEYRY4wiwxdeMNJpAqYQE/icVzzrN3MXJwsAioSrxr4gAJ8wq4 SSxqfckMsUxO4sOeR+wgNidQ/NP6dlaQciEBV4lnn+smMPIuYGRYxSiRWpBcUJyUnmuUl1qu V5yYW1yal66XnJ+7iRGcJJ5J72A8vMv9EKMAB6MSD++Ly1zhQqyJZcWVuYcYJTiYlUR4H8hy hwvxpiRWVqUW5ccXleakFh9iNAU6ayKzlGhyPjCB5ZXEGxqbmBlZGpkbWhgZmyuJ8z7+vy5M SCA9sSQ1OzW1ILUIpo+Jg1OqgdEuJHD5AdHDx5Ld5EpSBd1ms62/+eRgt0NFUodIgr3/XZfN czhSW/dfkRVRZDzW3Pr088wbr/IY4nUn3j0ub7peoeZo0Aq11yf0d6udVwu/lfY64jHTZL57 ydtV3JsvTk+JOnRvzYR5v20VHn4sY523es38HtnI5ruGKX+aFu23rV2dlNDCz6vEUpyRaKjF XFScCAA0d8zqKAMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl Tested-by: Anand Moon --- arch/arm/boot/dts/exynos4x12.dtsi | 106 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 99a0f4ca3d47..e5173107ed44 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -349,6 +349,112 @@ opp-hz = /bits/ 64 <267000000>; }; }; + + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_display: bus_display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + }; + + bus_peri: bus_peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus_mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_display_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + + bus_fsys_opp_table: opp_table5 { + compatible = "operating-points-v2"; + opp-shared; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp@134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + + bus_peri_opp_table: opp_table6 { + compatible = "operating-points-v2"; + opp-shared; + + opp@50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; }; &combiner {