From patchwork Mon Apr 11 07:42:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 8797311 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 273F19F3D1 for ; Mon, 11 Apr 2016 07:42:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B1DEC2022D for ; Mon, 11 Apr 2016 07:41:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6FAF820256 for ; Mon, 11 Apr 2016 07:41:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751310AbcDKHlg (ORCPT ); Mon, 11 Apr 2016 03:41:36 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:40157 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752857AbcDKHlH (ORCPT ); Mon, 11 Apr 2016 03:41:07 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5G01H09LCABPB0@mailout2.samsung.com>; Mon, 11 Apr 2016 16:40:58 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [203.254.230.47]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id E3.97.04804.A055B075; Mon, 11 Apr 2016 16:40:58 +0900 (KST) X-AuditID: cbfee690-f79e56d0000012c4-bc-570b550ad70b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id FC.3F.06699.9055B075; Mon, 11 Apr 2016 16:40:57 +0900 (KST) Received: from pankaj.sisodomain.com ([107.108.83.125]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O5G006QDLBXEB30@mmp2.samsung.com>; Mon, 11 Apr 2016 16:40:57 +0900 (KST) From: Pankaj Dubey To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, p.fedin@samsung.com, olof@lixom.net, thomas.ab@samsung.com, Pankaj Dubey , Kukjin Kim Subject: [RESPIN v2 4/6] ARM: EXYNOS: Remove SROM related register settings from mach-exynos Date: Mon, 11 Apr 2016 13:12:26 +0530 Message-id: <1460360548-32127-5-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1460360548-32127-1-git-send-email-pankaj.dubey@samsung.com> References: <1460360548-32127-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsVy+t8zfV2uUO5wg/mzWCxevzC06F1wlc2i //FrZotNj6+xWlzeNYfNYsb5fUwWp65/ZrN4dWkVm8WirV/YLTqWMTpweWxa1cnmsXlJvceV E02sHn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJWxrOMDU0GrTcWWHx4NjN1GXYycHBICJhKr l99nhLDFJC7cW8/WxcjFISSwklGi68xkJpiiM8ues4LYQgKzGCWOvi2GKPrJKDF36wywBJuA rsST93OZQWwRgWyJyWsfsYAUMQvsYpRYens9C0hCWCBOYnvbIaAiDg4WAVWJRXN8uhjZOXgF PCTuVEOskpM4eWwy2EROAU+Jzi03oNZ6SHx4tZgdZKKEwCZ2ieNb7rOBJFgEBCS+TT7EAjJR QkBWYtMBZog5khIHV9xgmcAovICRYRWjaGpBckFxUnqRiV5xYm5xaV66XnJ+7iZGSOBP2MF4 74D1IUYBDkYlHl6Ha1zhQqyJZcWVuYcYTYE2TGSWEk3OB8ZXXkm8obGZkYWpiamxkbmlmZI4 72upn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGIOnPAwWt24wffWiqlwhz3DfpRhNtbVG xy99jtqeKHbtefHbe9G8ripKfBwTBZLtTpiJ+mb//uqTaXV9pmrUe9mWL25Xt4bLVUm5niw+ EnFOZaNnl9ykuE+/Vze6zN92hoGby/PmnrAEWYnNvcFnz15aUf95701WppMtP2P+yh1JbMvx FLNZrMRSnJFoqMVcVJwIAC6KvGF3AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIIsWRmVeSWpSXmKPExsVy+t9jQV3OUO5wg10rbCxevzC06F1wlc2i //FrZotNj6+xWlzeNYfNYsb5fUwWp65/ZrN4dWkVm8WirV/YLTqWMTpweWxa1cnmsXlJvceV E02sHn1bVjF6fN4kF8Aa1cBok5GamJJapJCal5yfkpmXbqvkHRzvHG9qZmCoa2hpYa6kkJeY m2qr5OIToOuWmQN0k5JCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsI4xY1nH B6aCVpuKLT88Ghi7jboYOTkkBEwkzix7zgphi0lcuLeeDcQWEpjFKHH0bXEXIxeQ/ZNRYu7W GWBFbAK6Ek/ez2UGsUUEsiUmr33EAlLELLCLUWLp7fUsIAlhgTiJ7W2HgIo4OFgEVCUWzfHp YmTn4BXwkLhTDbFKTuLksclgEzkFPCU6t9xghVjrIfHh1WL2CYy8CxgZVjFKpBYkFxQnpeca 5aWW6xUn5haX5qXrJefnbmIER9cz6R2Mh3e5H2IU4GBU4uF9cZkrXIg1say4MvcQowQHs5II 74xA7nAh3pTEyqrUovz4otKc1OJDjKZAV01klhJNzgdGfl5JvKGxiZmRpZGZhZGJubmSOO/j /+vChATSE0tSs1NTC1KLYPqYODilGhgTlm3g35RTO/G+mcB2BSsdX8GtB7IifI7tFflwvu+S NMOvHZIJTzR3T4nPNz264sStK86zNDMD+xSaRScIKT+ZtVLwu7zhnTh3p+LHweG/q6sEwk6z b52bd9mT/YvapAdvZ5Y8YUm621N7gf/r/ao2RncOOz27r0sWxUpXtNtM/XMi3veHWrISS3FG oqEWc1FxIgB4n+kYxAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As now we have dedicated driver for SROM controller, it will take care of saving register banks during S2R so we can safely remove these settings from mach-exynos. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kukjin Kim [k.kozlowski: Need to select also SAMSUNG_MC] Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Kconfig | 3 ++ arch/arm/mach-exynos/exynos.c | 17 --------- arch/arm/mach-exynos/include/mach/map.h | 3 -- arch/arm/mach-exynos/regs-srom.h | 53 ---------------------------- arch/arm/mach-exynos/suspend.c | 20 ++--------- arch/arm/plat-samsung/include/plat/map-s5p.h | 1 - 6 files changed, 5 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/mach-exynos/regs-srom.h diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 207fa2c..28f9928 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -18,6 +18,7 @@ menuconfig ARCH_EXYNOS select COMMON_CLK_SAMSUNG select EXYNOS_THERMAL select EXYNOS_PMU + select EXYNOS_SROM if PM select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -26,11 +27,13 @@ menuconfig ARCH_EXYNOS select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC + select SAMSUNG_MC select SOC_SAMSUNG select SRAM select THERMAL select THERMAL_OF select MFD_SYSCON + select MEMORY select CLKSRC_EXYNOS_MCT select POWER_RESET select POWER_RESET_SYSCON diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index bbf51a4..f977eea 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -31,11 +31,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), .length = SZ_128K, @@ -58,15 +53,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; -static struct map_desc exynos5_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct platform_device exynos_cpuidle = { .name = "exynos_cpuidle", #ifdef CONFIG_ARM_EXYNOS_CPUIDLE @@ -138,9 +124,6 @@ static void __init exynos_map_io(void) { if (soc_is_exynos4()) iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); - - if (soc_is_exynos5()) - iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); } static void __init exynos_init_io(void) diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index c88325d..c48ba4f 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -25,7 +25,4 @@ #define EXYNOS4_PA_COREPERI 0x10500000 -#define EXYNOS4_PA_SROMC 0x12570000 -#define EXYNOS5_PA_SROMC 0x12250000 - #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h deleted file mode 100644 index 5c4d442..0000000 --- a/arch/arm/mach-exynos/regs-srom.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5P SROMC register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __PLAT_SAMSUNG_REGS_SROM_H -#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__ - -#include - -#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) - -#define S5P_SROM_BW S5P_SROMREG(0x0) -#define S5P_SROM_BC0 S5P_SROMREG(0x4) -#define S5P_SROM_BC1 S5P_SROMREG(0x8) -#define S5P_SROM_BC2 S5P_SROMREG(0xc) -#define S5P_SROM_BC3 S5P_SROMREG(0x10) -#define S5P_SROM_BC4 S5P_SROMREG(0x14) -#define S5P_SROM_BC5 S5P_SROMREG(0x18) - -/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ - -#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 -#define S5P_SROM_BW__ADDRMODE__SHIFT 1 -#define S5P_SROM_BW__WAITENABLE__SHIFT 2 -#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 - -#define S5P_SROM_BW__CS_MASK 0xf - -#define S5P_SROM_BW__NCS0__SHIFT 0 -#define S5P_SROM_BW__NCS1__SHIFT 4 -#define S5P_SROM_BW__NCS2__SHIFT 8 -#define S5P_SROM_BW__NCS3__SHIFT 12 -#define S5P_SROM_BW__NCS4__SHIFT 16 -#define S5P_SROM_BW__NCS5__SHIFT 20 - -/* applies to same to BCS0 - BCS3 */ - -#define S5P_SROM_BCX__PMC__SHIFT 0 -#define S5P_SROM_BCX__TACP__SHIFT 4 -#define S5P_SROM_BCX__TCAH__SHIFT 8 -#define S5P_SROM_BCX__TCOH__SHIFT 12 -#define S5P_SROM_BCX__TACC__SHIFT 16 -#define S5P_SROM_BCX__TCOS__SHIFT 24 -#define S5P_SROM_BCX__TACS__SHIFT 28 - -#endif /* __PLAT_SAMSUNG_REGS_SROM_H */ diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index fee2b00..f216909 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -34,10 +34,11 @@ #include #include +#include + #include #include "common.h" -#include "regs-srom.h" #define REG_TABLE_END (-1U) @@ -53,15 +54,6 @@ struct exynos_wkup_irq { u32 mask; }; -static struct sleep_save exynos_core_save[] = { - /* SROM side */ - SAVE_ITEM(S5P_SROM_BW), - SAVE_ITEM(S5P_SROM_BC0), - SAVE_ITEM(S5P_SROM_BC1), - SAVE_ITEM(S5P_SROM_BC2), - SAVE_ITEM(S5P_SROM_BC3), -}; - struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; @@ -343,8 +335,6 @@ static void exynos_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pm_enter_sleep_mode(); /* ensure at least INFORM0 has the resume address */ @@ -375,8 +365,6 @@ static void exynos5420_pm_prepare(void) /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); - s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3); /* * The cpu state needs to be saved and restored so that the @@ -467,8 +455,6 @@ static void exynos_pm_resume(void) /* For release retention */ exynos_pm_release_retention(); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -535,8 +521,6 @@ static void exynos5420_pm_resume(void) pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); - s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - early_wakeup: tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1); diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h index 4ec9a70..b63aeeb 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/plat-samsung/include/plat/map-s5p.h @@ -18,7 +18,6 @@ #define S5P_VA_DMC0 S3C_ADDR(0x02440000) #define S5P_VA_DMC1 S3C_ADDR(0x02480000) -#define S5P_VA_SROMC S3C_ADDR(0x024C0000) #define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000) #define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))