From patchwork Fri Apr 15 06:32:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 8845151 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 76F2A9FEF8 for ; Fri, 15 Apr 2016 06:33:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC37220138 for ; Fri, 15 Apr 2016 06:33:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB0D820379 for ; Fri, 15 Apr 2016 06:33:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753212AbcDOGdZ (ORCPT ); Fri, 15 Apr 2016 02:33:25 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:36025 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753164AbcDOGdV (ORCPT ); Fri, 15 Apr 2016 02:33:21 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5N025XJWUZSZ30@mailout3.samsung.com>; Fri, 15 Apr 2016 15:32:59 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.113]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id F0.9E.04789.B1B80175; Fri, 15 Apr 2016 15:32:59 +0900 (KST) X-AuditID: cbfee691-f795a6d0000012b5-49-57108b1b793d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 7F.93.06682.A1B80175; Fri, 15 Apr 2016 15:32:59 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O5N00MDZWUXF720@mmp2.samsung.com>; Fri, 15 Apr 2016 15:32:58 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, k.kozlowski@samsung.com, tomasz.figa@gmail.com, s.nawrocki@samsung.com, kgene@kernel.org Cc: robh@kernel.org, rjw@rjwysocki.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux.amoon@gmail.com, m.reichl@fivetechno.de, tjakobi@math.uni-bielefeld.de, inki.dae@samsung.com, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/8] dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC Date: Fri, 15 Apr 2016 15:32:52 +0900 Message-id: <1460701975-24178-6-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1460701975-24178-1-git-send-email-cw00.choi@samsung.com> References: <1460701975-24178-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAAy2SeUiTcRjH/W3vMYeLt6n1y4tYhGalecx+dkMoL2FQdAhF2NRXJ81rU7EI naWuvOZRmcO80DxahkvIhtU2JRCb94WmRlJqSkpbpSHW5vrv81zf7wPPw2HzjZgLJy4hhZEm iCQCgoupnQKTD7rmU+GHZvQcNG6ex1F1dx+OlMu1OOr71gxQ6WwxhpYW/JBybomNjHeWSaSZ G8PRsLaSQKbCboAe979loda2SRJNDfPQYvcaQA3jgyw0ldVEoOLy5xj60DuEo5w33ST629lB oq5lBY5yn63iqEW7AU5BWl2lBnT23QKCHi4qZNGTHzPp16ppkm5uNBO0puU+Qb+sz6Q335N0 +6gCo4vaWwBt0nicc7jCPRbNSOLSGKnvietccU1tO0jSbkvfNA+QcqBzyAP2HEgFQn31GG7j HXBg5gVhZT7VBOCmwjcPcLZ6TF8u29IqALVKzzzAtbAZwNn875i1QFDe8N3CBGEtOFEPAdTn q4A1YFOjbFiflUtalRypCDipumQdwKi9cPDPT2BlHhUCtUMrbNsSHnC18zNpZXsqFNaVjQOb cwjMrqraMoDUAAcWjfwGNiEK/iozYLZN3aFG919nF9Q3TWDFwLEG2LUAZyYpKkkWGSsV+shE 8bLUhFifqMR4DbBcuXfza0kHmNUdNQCKAwQOvE/XqHA+LkqT3Yw3AKHFoYTt4hyVaHmMhJQI v4AgfyQMFAb4Hw4OEuzkHXBdv8CnYkUpzA2GSWKkEdJUCSMzABbH3kUOrmaO1Z1dazsi7jk+ 6tz/Sukl32jIL+xBrSavkQfKjJzSR4YYcUM6e8+T8zG39jevR/cmdunvcfVuqW7Giv5pRc8Z 73L7RoKn97ztpquNDEvm23WERQt0Ellk6HzlaaMGPv2xUi4fpdX9iAmO2z5YWeE5X7AITO4n jRm7910UYDKxyM+bLZWJ/gERDiEA4AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNKsWRmVeSWpSXmKPExsVy+t9jQV3pboFwgx3fGS2uf3nOajH/yDlW i/43C1ktzr1ayWgx6f4EFovXLwwt+h+/ZrY42/SG3WLT42usFpd3zWGz+Nx7hNFixvl9TBbr Nt5it7h9mdfi5ZEfjBZLr19ksrjduILNYsL0tSwWZ05fYrVo3XuE3eL/nh3sFofftLNatK3+ wGqxatcfRgcJjzXz1jB6tDT3sHlc7utl8rh1p95j56y77B4rl39h89i0qpPNY/OSeo9/x9g9 tlxtZ/Ho27KK0ePzJrkAnqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8 xNxUWyUXnwBdt8wcoNeVFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqGBMH1GBmggYQ1jBkL Fm5hLNjFV/HvywX2BsYDPF2MHBwSAiYSn5+GdTFyApliEhfurWcDsYUEZjFK7OpX72LkArK/ MErc737HApJgE9CS2P/iBhtIQkRgKqPEwe5ZjCAOs8BVZokljW3sIFOFBeIlbs0KBWlgEVCV uPjrKyOIzSvgKrHr0ntmiG1yEh/2PGIHsTkF3CQWTb7OCLHZVaJl3jy2CYy8CxgZVjFKpBYk FxQnpeca5qWW6xUn5haX5qXrJefnbmIEJ4xnUjsYD+5yP8QowMGoxMP7IFYgXIg1say4MvcQ owQHs5II7+RWoBBvSmJlVWpRfnxRaU5q8SFGU6DDJjJLiSbnA5NZXkm8obGJmZGlkbmhhZGx uZI47+P/68KEBNITS1KzU1MLUotg+pg4OKUaGK984Hxqs8MmS1yxw7RCJ3Oi6L0Kxc+qAU/2 d7yfr3R80usnsff3zgh4tXCnl1ycvzvfEu/rC/asKLZICXoUK2p0obrwyNGEs4d/ZVf67jhR ENJxZdHcTV93KO5qt+a/fO3BidQjnl/sF+Vn2e2pKD6897LPiSjpYg69STuP2O1Zpb50KcvG liglluKMREMt5qLiRAA0UfqbLgMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the clock id for ACLK clock of Exynos542x SoC. ACLK clock mean the source clock of AMBA AXI bus. This clock id should be used for Bus frequency scaling. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Tested-by: Markus Reichl Tested-by: Anand Moon Reviewed-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos5420.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 7699ee9c16c0..17ab8394bec7 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -217,8 +217,30 @@ /* divider clocks */ #define CLK_DOUT_PIXEL 768 +#define CLK_DOUT_ACLK400_WCORE 769 +#define CLK_DOUT_ACLK400_ISP 770 +#define CLK_DOUT_ACLK400_MSCL 771 +#define CLK_DOUT_ACLK200 772 +#define CLK_DOUT_ACLK200_FSYS2 773 +#define CLK_DOUT_ACLK100_NOC 774 +#define CLK_DOUT_PCLK200_FSYS 775 +#define CLK_DOUT_ACLK200_FSYS 776 +#define CLK_DOUT_ACLK333_432_GSCL 777 +#define CLK_DOUT_ACLK333_432_ISP 778 +#define CLK_DOUT_ACLK66 779 +#define CLK_DOUT_ACLK333_432_ISP0 780 +#define CLK_DOUT_ACLK266 781 +#define CLK_DOUT_ACLK166 782 +#define CLK_DOUT_ACLK333 783 +#define CLK_DOUT_ACLK333_G2D 784 +#define CLK_DOUT_ACLK266_G2D 785 +#define CLK_DOUT_ACLK_G3D 786 +#define CLK_DOUT_ACLK300_JPEG 787 +#define CLK_DOUT_ACLK300_DISP1 788 +#define CLK_DOUT_ACLK300_GSCL 789 +#define CLK_DOUT_ACLK400_DISP1 790 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 769 +#define CLK_NR_CLKS 791 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */