From patchwork Wed May 11 12:02:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 9068321 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 25500BF440 for ; Wed, 11 May 2016 12:03:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B1A31201BB for ; Wed, 11 May 2016 12:03:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C97E0201B9 for ; Wed, 11 May 2016 12:03:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752455AbcEKMCn (ORCPT ); Wed, 11 May 2016 08:02:43 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:31543 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752249AbcEKMCk (ORCPT ); Wed, 11 May 2016 08:02:40 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O7000GHRHGCF250@mailout3.w1.samsung.com>; Wed, 11 May 2016 13:02:36 +0100 (BST) X-AuditID: cbfec7f5-f792a6d000001302-6a-57331f5cb1b8 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id C4.0B.04866.C5F13375; Wed, 11 May 2016 13:02:36 +0100 (BST) Received: from AMDC2174.DIGITAL.local ([106.120.53.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O7000965HG0RB60@eusync3.samsung.com>; Wed, 11 May 2016 13:02:36 +0100 (BST) From: Krzysztof Kozlowski To: Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , Kukjin Kim , Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz Subject: [PATCH 16/18] clk: samsung: exynos5420: Move sleep init function and PLL rates data to init section Date: Wed, 11 May 2016 14:02:12 +0200 Message-id: <1462968134-6085-16-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1462968134-6085-1-git-send-email-k.kozlowski@samsung.com> References: <1462968134-6085-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsVy+t/xq7ox8sbhBsfuqlpsnLGe1eL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxeE37awWP850s1is2vWH0YHb4/2NVnaP y329TB47Z91l99i0qpPNY/OSeo++LasYPT5vkgtgj+KySUnNySxLLdK3S+DKmH9tHlvBdp6K Jz0NbA2MZ7m6GDk5JARMJF5MWMYKYYtJXLi3nq2LkYtDSGApo8SFY+sZIZxGJonNm7azg1Sx CRhLbF6+BKxKRKCJWeLBrhZmkASzgIXE1q2rwYqEBfIkFnw5wwRiswioSmw5CDKJk4NXwF3i 3sLNLBDr5CROHpsMtpoTKH573SGgeg6gbW4Sz75zT2DkXcDIsIpRNLU0uaA4KT3XSK84Mbe4 NC9dLzk/dxMjJBi/7mBceszqEKMAB6MSD++GKqNwIdbEsuLK3EOMEhzMSiK8c2WNw4V4UxIr q1KL8uOLSnNSiw8xSnOwKInzztz1PkRIID2xJDU7NbUgtQgmy8TBKdXAmP0nTL9Jzc3TuELT ZtHav4UiG01mH7v/ojt92Zu5XhW9pl2nSx4vv8doN7GqPCdQ4SVrTGb1jS2PjlR3xS5KZz50 ZmbtxAn7A2sPfwkpPH7EtX1eWMZPQeOLml9F+ZbMf3E14zvP2msS56Jqq5/5Hfl9ei9/5sfV k/9zOLy65Photkdi75R4JiWW4oxEQy3mouJEAPFo/1RCAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The exynos5420_clk_sleep_init() function and arrays with initialization data of PLLs can be moved to init section because they are referenced only from other init-level symbols. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5420.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index adb0ae4efb7a..79fb8557bcf3 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -306,7 +306,7 @@ static struct syscore_ops exynos5420_clk_syscore_ops = { .resume = exynos5420_clk_resume, }; -static void exynos5420_clk_sleep_init(void) +static void __init exynos5420_clk_sleep_init(void) { exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs)); @@ -333,7 +333,7 @@ err_soc: return; } #else -static void exynos5420_clk_sleep_init(void) {} +static void __init exynos5420_clk_sleep_init(void) {} #endif /* list of all parent clocks */ @@ -1219,7 +1219,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), }; -static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { +static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { PLL_35XX_RATE(2000000000, 250, 3, 0), PLL_35XX_RATE(1900000000, 475, 6, 0), PLL_35XX_RATE(1800000000, 225, 3, 0),