From patchwork Wed Jun 15 14:13:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 9178631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2B95A608A2 for ; Wed, 15 Jun 2016 14:27:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1CC2B27DCE for ; Wed, 15 Jun 2016 14:27:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1056A27F3E; Wed, 15 Jun 2016 14:27:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9026327E71 for ; Wed, 15 Jun 2016 14:27:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161168AbcFOO1h (ORCPT ); Wed, 15 Jun 2016 10:27:37 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:60232 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1161125AbcFOO1a (ORCPT ); Wed, 15 Jun 2016 10:27:30 -0400 Received: from hkpgpgate102.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate101.nvidia.com id ; Wed, 15 Jun 2016 22:27:24 +0800 Received: from HKMAIL101.nvidia.com ([10.18.67.137]) by hkpgpgate102.nvidia.com (PGP Universal service); Wed, 15 Jun 2016 07:27:22 -0700 X-PGP-Universal: processed; by hkpgpgate102.nvidia.com on Wed, 15 Jun 2016 07:27:22 -0700 Received: from DRBGMAIL102.nvidia.com (10.18.16.21) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 15 Jun 2016 14:27:21 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by DRBGMAIL102.nvidia.com (10.18.16.21) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 15 Jun 2016 14:27:19 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 15 Jun 2016 14:27:15 +0000 From: Laxman Dewangan To: , , , , CC: , , , , , Laxman Dewangan , Javier Martinez Canillas Subject: [PATCH 4/5] clk: max77686: Add support for MAX77620 clocks Date: Wed, 15 Jun 2016 19:43:37 +0530 Message-ID: <1466000018-16784-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466000018-16784-1-git-send-email-ldewangan@nvidia.com> References: <1466000018-16784-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Maxim Max77620 has one 32KHz clock output and the clock HW IP used on this PMIC is same as what it is there in the MAX77686. Add clock driver support for MAX77620 on the MAX77686 driver. Signed-off-by: Laxman Dewangan CC: Krzysztof Kozlowski CC: Javier Martinez Canillas Reviewed-by: Javier Martinez Canillas Tested-by: Krzysztof Kozlowski --- drivers/clk/Kconfig | 7 ++++--- drivers/clk/clk-max77686.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6afad74..d75f4c5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -32,10 +32,11 @@ config COMMON_CLK_WM831X source "drivers/clk/versatile/Kconfig" config COMMON_CLK_MAX77686 - tristate "Clock driver for Maxim 77686/77802 MFD" - depends on MFD_MAX77686 + tristate "Clock driver for Maxim 77686/77802/MAX77620 MFD" + depends on MFD_MAX77686 || MFD_MAX77620 ---help--- - This driver supports Maxim 77686/77802 crystal oscillator clock. + This driver supports Maxim 77686/77802/MAX77620 crystal oscillator + clock. config COMMON_CLK_RK808 tristate "Clock driver for RK808" diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 31ba726..d2be736 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -30,12 +31,14 @@ #include #include +#include #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3 enum chip_name { CHIP_MAX77686, CHIP_MAX77802, + CHIP_MAX77620, }; struct max_gen_hw_clk_data { @@ -91,6 +94,14 @@ static struct max_gen_hw_clk_data max77802_hw_clks_info[MAX77802_CLKS_NUM] = { }, }; +static struct max_gen_hw_clk_data max77620_hw_clks_info[MAX77620_CLKS_NUM] = { + [MAX77620_CLK_32K_OUT0] = { + .name = "32khz_pmic", + .reg = MAX77620_REG_CNFG1_32K, + .mask = MAX77620_CNFG1_32K_OUT0_EN, + }, +}; + static struct max_gen_clk_data *to_max_gen_clk_data(struct clk_hw *hw) { return container_of(hw, struct max_gen_clk_data, hw); @@ -171,6 +182,10 @@ static int max77686_clk_probe(struct platform_device *pdev) num_clks = MAX77802_CLKS_NUM; hw_clks = max77802_hw_clks_info; break; + case CHIP_MAX77620: + num_clks = MAX77620_CLKS_NUM; + hw_clks = max77620_hw_clks_info; + break; default: dev_err(dev, "Unknown Chip ID\n"); return -EINVAL; @@ -269,6 +284,7 @@ static int max77686_clk_remove(struct platform_device *pdev) static const struct platform_device_id max77686_clk_id[] = { { "max77686-clk", .driver_data = (kernel_ulong_t)CHIP_MAX77686, }, { "max77802-clk", .driver_data = (kernel_ulong_t)CHIP_MAX77802, }, + { "max77620-clock", .driver_data = (kernel_ulong_t)CHIP_MAX77620, }, {}, }; MODULE_DEVICE_TABLE(platform, max77686_clk_id);