From patchwork Tue Jul 5 20:29:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 9214813 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E8B716048B for ; Tue, 5 Jul 2016 16:26:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D6BAF2756B for ; Tue, 5 Jul 2016 16:26:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CB429275A2; Tue, 5 Jul 2016 16:26:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_03_06, DKIM_SIGNED,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 429362756B for ; Tue, 5 Jul 2016 16:26:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752533AbcGEQWN (ORCPT ); Tue, 5 Jul 2016 12:22:13 -0400 Received: from mail-pa0-f65.google.com ([209.85.220.65]:35936 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755292AbcGEQWL (ORCPT ); Tue, 5 Jul 2016 12:22:11 -0400 Received: by mail-pa0-f65.google.com with SMTP id ib6so2725665pad.3; Tue, 05 Jul 2016 09:22:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DkpNhUgZs50N0kLhX0tDjr5lUNHdgbqH2kxbhwbdrNI=; b=R9WobyzGkjNKWDb8CFEf3SJa6CAPtTTS3Iyqmbp+nH9c28Vf/Gi2g554FcUalznoJi TOC8zZQPU+LUq0FRR1wsFd+8u951FJMBWcNbvRe6Lr3OIY9LuCwnseYc9h4U88i9V6Oh bnAjaP+LV+ni5lQlO5UX+SH5Pv9O4vWeS8mS+AmsfB8I1qZpcx3Y9br72LKatdQtBpB2 nKo7l90OCLHmPUyZBuVokKaiWKuOIkBcdybQr5qzajC60pMOUYxuPfOskEmEl+oY3+ZQ sktebEkO+dIezYWtPFQWJUwG/17F4LdfdTgsBEQP1KM564O8lc21oWjMALgN4dnIXX31 1BYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=DkpNhUgZs50N0kLhX0tDjr5lUNHdgbqH2kxbhwbdrNI=; b=KUpUUlnDzYVF14OvJVCRQholML3fFcHHXEKQDHRq+ZVhVqt2w30L8948iwbfLOoeoR IHmL6K+/xH2zgReN7EXKlewa3Oj/TnachGXz/P5KCew/biT9NPCPGJiW/F4q2A1g8ns2 TGtTaX9D6DL6r9tiujvG+xJ9k/a67IOtZztqImu/RM2FNp+Xtn6QE8rm8MLe6NfpgMaB zjXDRi/RfM8QEDMISjM+gH/9eyO3a+GHuhXzQ6ycJ/ece5/uJh9haWavwKGjIiejhh75 CDn6r0OmlAON6iqSDQYGaON595S1XR8W/5oNlkfJ/1I3XlEdPxXUJZ7ojTpvBR8LkaJ9 9lGg== X-Gm-Message-State: ALyK8tIcktTvhpx68iqBCYblWV0RUSpAVwdfxe37/hps1bJ16Ix9POq3HgraPZtHbj6LyQ== X-Received: by 10.67.7.71 with SMTP id da7mr33148958pad.136.1467735730834; Tue, 05 Jul 2016 09:22:10 -0700 (PDT) Received: from localhost.localdomain ([180.151.249.230]) by smtp.gmail.com with ESMTPSA id zv2sm6524644pac.43.2016.07.05.09.22.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Jul 2016 09:22:10 -0700 (PDT) From: Abhilash Kesavan To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, b.zolnierkie@samsung.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] clk: samsung: cpu: Prepare for addition for Exynos7 CPU clocks Date: Wed, 6 Jul 2016 01:59:20 +0530 Message-Id: <1467750561-13957-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1467750561-13957-1-git-send-email-a.kesavan@samsung.com> References: <1467750561-13957-1-git-send-email-a.kesavan@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos7 has the same CPU clock registers layout as that present in Exynos5433 except for the bits in the MUX_STAT* registers. Add a new CLK_CPU_HAS_MODIFIED_MUX_STAT flag to handle this change. Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-cpu.c | 10 ++++++++-- drivers/clk/samsung/clk-cpu.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 8bf7e80..d40d740 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -322,7 +322,10 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* select the alternate parent */ mux_reg = readl(base + E5433_MUX_SEL2); writel(mux_reg | 1, base + E5433_MUX_SEL2); - wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2); + if (cpuclk->flags & CLK_CPU_HAS_MODIFIED_MUX_STAT) + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); + else + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2); /* alternate parent is active now. set the dividers */ writel(div0, base + E5433_DIV_CPU0); @@ -348,7 +351,10 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, /* select apll as the alternate parent */ mux_reg = readl(base + E5433_MUX_SEL2); writel(mux_reg & ~1, base + E5433_MUX_SEL2); - wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); + if (cpuclk->flags & CLK_CPU_HAS_MODIFIED_MUX_STAT) + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 0); + else + wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); exynos5433_set_safe_div(base, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags); diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index d4b6b51..b4d9a4b 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -63,6 +63,8 @@ struct exynos_cpuclk { #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) /* The CPU clock registers have Exynos5433-compatible layout */ #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) +/* Exynos5433-compatible layout with different MUX_STAT register bits */ +#define CLK_CPU_HAS_MODIFIED_MUX_STAT (1 << 3) }; extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,