From patchwork Thu Aug 25 06:57:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 9298763 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 16E3860459 for ; Thu, 25 Aug 2016 07:00:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07FB428F82 for ; Thu, 25 Aug 2016 07:00:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EFF46291F7; Thu, 25 Aug 2016 07:00:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91E2128F82 for ; Thu, 25 Aug 2016 07:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756747AbcHYG7J (ORCPT ); Thu, 25 Aug 2016 02:59:09 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:35949 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756273AbcHYG7I (ORCPT ); Thu, 25 Aug 2016 02:59:08 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OCG00OAMDZOFGE0@mailout4.samsung.com>; Thu, 25 Aug 2016 15:57:24 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.113]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 1A.D3.27902.4D69EB75; Thu, 25 Aug 2016 15:57:24 +0900 (KST) X-AuditID: cbfee68e-f79cb6d000006cfe-c6-57be96d481b1 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 20.A2.05218.4D69EB75; Thu, 25 Aug 2016 15:57:24 +0900 (KST) Received: from chan.10.32.193.11 ([10.113.62.212]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OCG007BZDZNHZ00@mmp1.samsung.com>; Thu, 25 Aug 2016 15:57:23 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, chanwoo@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chanwoo Choi Subject: [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Date: Thu, 25 Aug 2016 15:57:18 +0900 Message-id: <1472108238-24309-4-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> References: <1472108238-24309-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsWyRsSkUPfKtH3hBjvXiFlMvHGFxeL6l+es Fq9fGFr0P37NbLHp8TVWi48991gtLu+aw2Yx4/w+JouLp1wtDr9pZ7X4caabxWLVrj+MDjwe 72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7FJdNSmpOZllqkb5dAlfG7PdT WQpOc1VM/fmKvYFxM3sXIyeHhICJxKytu5khbDGJC/fWs3UxcnEICaxglFjwZDdc0a2ukywQ iaWMEsvmL2CEcL4wSrzo+wTWziagJbH/xQ2gdg4OEQFDiZuHlEDCzAILmCQ6NoENEhZIkXh6 eAUriM0ioCqx9P5aMJtXwFViw8vprBDL5CQ+7HkEVs8p4CYxZc4CJhBbCKhmyffrYHslBM6x S7y+cIQJYpCAxLfJh1hA9koIyEpsOgD1jaTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKRXnJhb XJqXrpecn7uJERgnp/8969vBePOA9SFGAQ5GJR7eHav2hguxJpYVV+YeYjQF2jCRWUo0OR8Y jXkl8YbGZkYWpiamxkbmlmZK4rwJUj+DhQTSE0tSs1NTC1KL4otKc1KLDzEycXBKNTAKRfRN Zn4aEDwjgb30imK8jX9RRtiDc00bJnBonNzanPNa45vfun7tR/PNWWaGXPwcUaC2+twVZd+j rm8VeFaKmUz9ZiO95u2h47V5U8x6rPNO9TyVe9uvtmDry1C2yKX6bPL6NwplLbOOr0m40LIs tNet+b09y8GVG9mYt9pe5JhpVLnK2liJpTgj0VCLuag4EQCgEmpdjgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBIsWRmVeSWpSXmKPExsVy+t9jAd0r0/aFG6x7LWAx8cYVFovrX56z Wrx+YWjR//g1s8Wmx9dYLT723GO1uLxrDpvFjPP7mCwunnK1OPymndXix5luFotVu/4wOvB4 vL/Ryu5xua+XyWPnrLvsHptWdbJ5bF5S79G3ZRWjx+dNcgHsUQ2MNhmpiSmpRQqpecn5KZl5 6bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAdyoplCXmlAKFAhKLi5X07TBNCA1x 07WAaYzQ9Q0JgusxMkADCWsYM2a/n8pScJqrYurPV+wNjJvZuxg5OSQETCRudZ1kgbDFJC7c W8/WxcjFISSwlFFi2fwFjBDOF0aJF32fmEGq2AS0JPa/uAFUxcEhImAocfOQEkiYWWABk0TH JrChwgIpEk8Pr2AFsVkEVCWW3l8LZvMKuEpseDmdFWKZnMSHPY/A6jkF3CSmzFnABGILAdUs +X6dcQIj7wJGhlWMEqkFyQXFSem5hnmp5XrFibnFpXnpesn5uZsYwbH4TGoH48Fd7ocYBTgY lXh4DUT2hQuxJpYVV+YeYpTgYFYS4T00GSjEm5JYWZValB9fVJqTWnyI0RTosInMUqLJ+cA0 kVcSb2hsYmZkaWRuaGFkbK4kzvv4/7owIYH0xJLU7NTUgtQimD4mDk6pBkbFvR3SVz0PrTm+ 0nuGsu6rvO/vPsfd32ei+O7ya/6bp746G7bq13+YcO67WzL79qCG0NwYjWppTcXoD9GSTzxO f3e6udR+cszpS1M90k69Y/hU+F2Vs0H8tkum7ioboe+GiVf7+vhWJi3etmO2m79Uxba9G/Vl ptmZuM9fI/dJNVUtc0dz/GQlluKMREMt5qLiRABhvyJ+2wIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sets the clock rate for DREX (DRAM Express) block on exynos5422-odroidxu3 board. In the exynos5422 TRM, DRAM clocks use BPLL clock and CMU_CDREX generates the 800MHz DRAM clock. [clk_summary on exynos5422-odroidxu3 board] fout_bpll 0 0 800000000 0 0 mout_bpll 0 0 800000000 0 0 mout_mclk_cdrex 0 0 800000000 0 0 dout_pclk_core_mem 0 0 200000000 0 0 dout_sclk_cdrex 0 0 800000000 0 0 Signed-off-by: Chanwoo Choi --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccb..fd3f67c72039 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -229,6 +229,11 @@ status = "okay"; }; +&clock { + assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>; + assigned-clock-rates = <800000000>; +}; + &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_I2S>,