From patchwork Thu Sep 1 07:23:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 9308449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5745460756 for ; Thu, 1 Sep 2016 07:24:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49D172921A for ; Thu, 1 Sep 2016 07:24:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E32C2921D; Thu, 1 Sep 2016 07:24:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 906222921A for ; Thu, 1 Sep 2016 07:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753332AbcIAHYT (ORCPT ); Thu, 1 Sep 2016 03:24:19 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:43056 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752725AbcIAHYR (ORCPT ); Thu, 1 Sep 2016 03:24:17 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OCT007JMDWCOA20@mailout4.w1.samsung.com>; Thu, 01 Sep 2016 08:24:12 +0100 (BST) X-AuditID: cbfec7f4-f79cb6d000001359-c4-57c7d79cdeb9 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 68.0A.04953.C97D7C75; Thu, 1 Sep 2016 08:24:12 +0100 (BST) Received: from AMDC2174.DIGITAL.local ([106.120.53.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OCT00GQQDW8E630@eusync3.samsung.com>; Thu, 01 Sep 2016 08:24:12 +0100 (BST) From: Krzysztof Kozlowski To: Tomasz Figa , Krzysztof Kozlowski , Sylwester Nawrocki , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Kukjin Kim Cc: Arnd Bergmann , javier@osg.samsung.com, Linus Walleij , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v2 01/10] pinctrl: dt-bindings: samsung: Add header with values used for configuration Date: Thu, 01 Sep 2016 09:23:49 +0200 Message-id: <1472714638-15676-2-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1472714638-15676-1-git-send-email-k.kozlowski@samsung.com> References: <1472714638-15676-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsVy+t/xq7pzrh8PN7j0Tdvi76Rj7BYbZ6xn tZh/5ByrxZu3a5gsXr8wtOh//JrZ4vz5DewWU/4sZ7LY9Pgaq8XlXXPYLGac38dksfT6RSaL 1r1H2C0Ov2lntVi16w+jA7/HmnlrGD1+/5rE6LFz1l12j02rOtk87lzbw+axeUm9x5Z+oFDf llWMHp83yQVwRnHZpKTmZJalFunbJXBlHD+xjrHgn3jFwjmfmBsYe0W6GDk5JARMJOZNvsoG YYtJXLi3Hsjm4hASWMoo0bX+GzuE08gkcXT/XUaQKjYBY4nNy5eAVYkIvGGS+Ne6gRHEYRY4 xyjx5PITsFnCAhkSRw+uB+tgEVCVOHBxAjOIzSvgLvFixkYmiH1yEiePTWYFsTkFPCRm3vnP DmILAdWsOPGDeQIj7wJGhlWMoqmlyQXFSem5hnrFibnFpXnpesn5uZsYIeH8ZQfj4mNWhxgF OBiVeHgd3hwLF2JNLCuuzD3EKMHBrCTCq3zpeLgQb0piZVVqUX58UWlOavEhRmkOFiVx3rm7 3ocICaQnlqRmp6YWpBbBZJk4OKUaGIteHqoPYo35oaBo5J1wdk/hxmrraIZZ31P7f67jU/P+ pLFF5sOi3O3PRMJj7dOlryg/PyP96KlbgucjicojFuc6jjl22ZdZKAhP5jk2594F9ilCm7/N D17YkH1jp6PikwvPJj5lKfkRf/+a+uSlvG1fZa+ktU36aXz6bXLDJM8LsT+U3tzeq63EUpyR aKjFXFScCAC+IOo3YwIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hard-coded pinctrl configuration values are scattered through DTS files. The numbers are difficult to decode by human, especially without the datasheet. Additionally the drive strength differs between Exynos SoC families increasing the confusion. The header will help making this more readable and maintainable. Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 1 + include/dt-bindings/pinctrl/samsung.h | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/dt-bindings/pinctrl/samsung.h diff --git a/MAINTAINERS b/MAINTAINERS index d8e81b1dde30..836bcd327ee4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9318,6 +9318,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) S: Maintained F: drivers/pinctrl/samsung/ +F: include/dt-bindings/pinctrl/samsung.h PIN CONTROLLER - SINGLE M: Tony Lindgren diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h new file mode 100644 index 000000000000..0f410ba5ec7e --- /dev/null +++ b/include/dt-bindings/pinctrl/samsung.h @@ -0,0 +1,57 @@ +/* + * Samsung's Exynos pinctrl bindings + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Author: Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DT_BINDINGS_PINCTRL_EXYNOS_H__ +#define __DT_BINDINGS_PINCTRL_EXYNOS_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYONS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_F 0xf + +#endif /* __DT_BINDINGS_PINCTRL_EXYNOS_H__ */