From patchwork Tue Oct 18 06:21:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zain Wang X-Patchwork-Id: 9381339 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 587D8600CA for ; Tue, 18 Oct 2016 06:22:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4BD5A2939A for ; Tue, 18 Oct 2016 06:22:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3FAB82939F; Tue, 18 Oct 2016 06:22:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B46022939A for ; Tue, 18 Oct 2016 06:22:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755224AbcJRGWV (ORCPT ); Tue, 18 Oct 2016 02:22:21 -0400 Received: from regular1.263xmail.com ([211.150.99.140]:48118 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751350AbcJRGWU (ORCPT ); Tue, 18 Oct 2016 02:22:20 -0400 Received: from wzz?rock-chips.com (unknown [192.168.167.156]) by regular1.263xmail.com (Postfix) with ESMTP id 360284DAD; Tue, 18 Oct 2016 14:22:13 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 7ACC6420; Tue, 18 Oct 2016 14:22:08 +0800 (CST) X-RL-SENDER: wzz@rock-chips.com X-FST-TO: seanpaul@chromium.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: wzz@rock-chips.com X-UNIQUE-TAG: <3161a31e9f94ddae01c3c6dc9404f413> X-ATTACHMENT-NUM: 0 X-SENDER: zain.wang@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 26760XX3QOM; Tue, 18 Oct 2016 14:22:13 +0800 (CST) From: Zain Wang To: Sean Paul , Daniel Vetter , Inki Dae , David Airlie Cc: Tomeu Vizoso , Mika Kahola , =?UTF-8?q?St=C3=A9phane=20Marchesin?= , Tomasz Figa , dianders@chromium.org, Thierry Reding , Krzysztof Kozlowski , Heiko Stuebner , Jingoo Han , Javier Martinez Canillas , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, zain wang Subject: [PATCH v3 4/6] drm: bridge/analogix: switch Main-link and eDP PHY when enable/disable psr Date: Tue, 18 Oct 2016 14:21:59 +0800 Message-Id: <1476771719-11941-1-git-send-email-wzz@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: zain wang turn off Main-link and power down eDP PHY when enable psr, turn on Main-link and power up eDP PHY when disable psr. Signed-off-by: zain wang --- Changes in v3: - detecting PSR state at enable/disable_psr() avoid to make link training when sink in not PSR State. Changes in v2: - misc changes drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 123 +++++++++++++-------- 1 file changed, 76 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index c4f139a..c662e5d 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -98,50 +98,6 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) return 0; } -int analogix_dp_enable_psr(struct device *dev) -{ - struct analogix_dp_device *dp = dev_get_drvdata(dev); - struct edp_vsc_psr psr_vsc; - - if (!dp->psr_support) - return -EINVAL; - - /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ - memset(&psr_vsc, 0, sizeof(psr_vsc)); - psr_vsc.sdp_header.HB0 = 0; - psr_vsc.sdp_header.HB1 = 0x7; - psr_vsc.sdp_header.HB2 = 0x2; - psr_vsc.sdp_header.HB3 = 0x8; - - psr_vsc.DB0 = 0; - psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; - - return analogix_dp_send_psr_spd(dp, &psr_vsc); -} -EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); - -int analogix_dp_disable_psr(struct device *dev) -{ - struct analogix_dp_device *dp = dev_get_drvdata(dev); - struct edp_vsc_psr psr_vsc; - - if (!dp->psr_support) - return -EINVAL; - - /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ - memset(&psr_vsc, 0, sizeof(psr_vsc)); - psr_vsc.sdp_header.HB0 = 0; - psr_vsc.sdp_header.HB1 = 0x7; - psr_vsc.sdp_header.HB2 = 0x2; - psr_vsc.sdp_header.HB3 = 0x8; - - psr_vsc.DB0 = 0; - psr_vsc.DB1 = 0; - - return analogix_dp_send_psr_spd(dp, &psr_vsc); -} -EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); - static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) { unsigned char psr_version; @@ -162,12 +118,11 @@ static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); /* Main-Link transmitter remains active during PSR active states */ - psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; + psr_en = DP_PSR_CRC_VERIFICATION; drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); /* Enable psr function */ - psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | - DP_PSR_CRC_VERIFICATION; + psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION; drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en); analogix_dp_enable_psr_crc(dp); @@ -870,6 +825,80 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_sink_psr(dp); } +int analogix_dp_enable_psr(struct device *dev) +{ + struct analogix_dp_device *dp = dev_get_drvdata(dev); + struct edp_vsc_psr psr_vsc; + int retval; + u8 sink; + + if (!dp->psr_support) + return -EINVAL; + + drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink); + if (sink == DP_PSR_SINK_ACTIVE_RFB) + return 0; + + /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ + memset(&psr_vsc, 0, sizeof(psr_vsc)); + psr_vsc.sdp_header.HB0 = 0; + psr_vsc.sdp_header.HB1 = 0x7; + psr_vsc.sdp_header.HB2 = 0x2; + psr_vsc.sdp_header.HB3 = 0x8; + + psr_vsc.DB0 = 0; + psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; + + retval = analogix_dp_send_psr_spd(dp, &psr_vsc); + + if (!retval) { + /* Power down the eDP PHY */ + analogix_dp_set_analog_power_down(dp, POWER_ALL, true); + } + + return retval; +} +EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); + +int analogix_dp_disable_psr(struct device *dev) +{ + struct analogix_dp_device *dp = dev_get_drvdata(dev); + struct edp_vsc_psr psr_vsc; + int ret; + u8 sink; + + if (!dp->psr_support) + return -EINVAL; + + /* Power up the eDP PHY */ + analogix_dp_set_analog_power_down(dp, POWER_ALL, false); + + drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink); + if (sink == DP_PSR_SINK_INACTIVE) + return 0; + + ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0); + if (ret < 0) { + dev_err(dp->dev, "Failed to set DP Power0\n"); + } + + analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, + dp->video_info.max_link_rate); + + /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ + memset(&psr_vsc, 0, sizeof(psr_vsc)); + psr_vsc.sdp_header.HB0 = 0; + psr_vsc.sdp_header.HB1 = 0x7; + psr_vsc.sdp_header.HB2 = 0x2; + psr_vsc.sdp_header.HB3 = 0x8; + + psr_vsc.DB0 = 0; + psr_vsc.DB1 = 0; + + return analogix_dp_send_psr_spd(dp, &psr_vsc); +} +EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); + /* * This function is a bit of a catch-all for panel preparation, hopefully * simplifying the logic of functions that need to prepare/unprepare the panel