From patchwork Fri Dec 9 07:22:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 9467645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9B9B8607D6 for ; Fri, 9 Dec 2016 07:22:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DAF2285BA for ; Fri, 9 Dec 2016 07:22:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80AFE28610; Fri, 9 Dec 2016 07:22:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27AA5285BA for ; Fri, 9 Dec 2016 07:22:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753276AbcLIHWj (ORCPT ); Fri, 9 Dec 2016 02:22:39 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:52418 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751983AbcLIHWj (ORCPT ); Fri, 9 Dec 2016 02:22:39 -0500 Received: from epcpsbgm2new.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OHW013BJPTP1R10@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 09 Dec 2016 16:22:37 +0900 (KST) X-AuditID: cbfee61b-f796f6d000004092-52-584a5bbd59fe Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id E3.07.16530.DBB5A485; Fri, 9 Dec 2016 16:22:37 +0900 (KST) Received: from AMDC2765.digital.local ([106.116.147.25]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OHW0089XPT1YI30@mmp2.samsung.com>; Fri, 09 Dec 2016 16:22:36 +0900 (KST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 2/2] ARM: dts: exynos: Fix initial audio clocks configuration on Exynos4 boards Date: Fri, 09 Dec 2016 08:22:11 +0100 Message-id: <1481268131-1264-2-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1481268131-1264-1-git-send-email-m.szyprowski@samsung.com> References: <1481268131-1264-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsVy+t9jQd290V4RBjvOS1tsnLGe1eL6l+es FufPb2C3mHF+H5PF2iN32S0Ov2lndWDz2LSqk82jb8sqRo/Pm+QCmKPcbDJSE1NSixRS85Lz UzLz0m2VQkPcdC2UFPISc1NtlSJ0fUOClBTKEnNKgTwjAzTg4BzgHqykb5fglnH98FnGgquS FZMfbGRuYNwt2sXIySEhYCLxqXsGG4QtJnHh3nogm4tDSGAWo8TSxd/YIZxfjBLfJu1lAqli EzCU6HrbBdYhIqAq8bltAVgRs8BzRon3u/tZQBLCAikSjU9uATVwcLAAFd18GQsS5hVwl1g5 Zy4rxDY5iZPHJoPZnAIeEp2vrrCBlAsB1Uw8IDiBkXcBI8MqRonUguSC4qT0XKO81HK94sTc 4tK8dL3k/NxNjOCgfSa9g/HwLvdDjAIcjEo8vAcKPCOEWBPLiitzDzFKcDArifCeiPKKEOJN SaysSi3Kjy8qzUktPsRoCnTWRGYp0eR8YETllcQbmpibmBsbWJhbWpoYKYnzNs5+Fi4kkJ5Y kpqdmlqQWgTTx8TBKdXAGOjwJk5rr5jnvBUaHrPc22/83K316OanwMnLA952L61lr15VxxPM wuTvYbT9vPFjpk9zYvzLPikLfC6LWXdoubpk7YFfsbsvvLWZ3JlV6yKg9njDTG+Pgt49rw6Z 3TI+654c9yNcWcj3yoT9z7fofXeq7vMSmn/owaTO8CvXUw8XG3uJXp4uoMRSnJFoqMVcVJwI ACIHAGdwAgAA X-MTR: 20000000000000000@CPGS Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move assigned clocks properties from sound node to audio subsystem clock controller node. This way clocks topology and rates are set just after probing audio clocks controller. Leaving those properties under sound node doesn't guarantee to configure them before they are being used (for example i2s hardware module can be probed in parallel and it also require proper audio clocks configuration). Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- Changelog: v2: - added changes for exynos4412-itop-elite board --- arch/arm/boot/dts/exynos4412-itop-elite.dts | 21 ++++++++++----------- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 20 ++++++++++---------- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 1ac9129..d660930 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -82,17 +82,6 @@ compatible = "simple-audio-card"; simple-audio-card,name = "wm-sound"; - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <112896000>, - <11289600>; - simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&link0_codec>; simple-audio-card,frame-master = <&link0_codec>; @@ -145,6 +134,16 @@ status = "okay"; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, <0>, <112896000>, <11289600>; +}; + &ehci { status = "okay"; /* In order to reset USB ethernet */ diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 7815efd..b6b0f50 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -43,16 +43,6 @@ sound: sound { compatible = "simple-audio-card"; - assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>; - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <192000000>, - <19200000>; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&link0_codec>; @@ -157,6 +147,16 @@ status = "okay"; }; +&clock_audss { + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, <0>, <192000000>, <19200000>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; };