@@ -32,6 +32,7 @@
#include <trace/events/power.h>
#include <linux/cpufreq.h>
#include <linux/cpuidle.h>
+#include <linux/devfreq.h>
#include <linux/timer.h>
#include "../base.h"
@@ -943,6 +944,7 @@ void dpm_resume(pm_message_t state)
dpm_show_time(starttime, state, NULL);
cpufreq_resume();
+ devfreq_resume();
trace_suspend_resume(TPS("dpm_resume"), state.event, false);
}
@@ -1582,6 +1584,7 @@ int dpm_suspend(pm_message_t state)
trace_suspend_resume(TPS("dpm_suspend"), state.event, true);
might_sleep();
+ devfreq_suspend();
cpufreq_suspend();
mutex_lock(&dpm_list_mtx);
On the Exynos4412 SoC the DevFreq subsystem adjusts the frequency of the various internal busses and the corresponding voltages. E.g. the clock of the DMC (dynamic memory controller) bus together with the voltage of the MIF regulator are controlled by this. If DMC activity is low and DevFreq has set a lower OPP, the following can happen. The transition to the lower OPP has set a voltage V_low. If the system now is restarted or goes into a suspend/resume-cycle, the first-stage (BL0) bootloader takes over, which also initializes clocks to default values, say freq_0 for the DMC. Since the PMIC is an external component and not part of the SoC, the BL0 doesn't set any default voltages. The BL0 now hangs because the required voltage V_0 (corresponding to freq_0) is higher than the currently set one V_low. To fix this, we make sure to only go into suspend with a 'safe' DevFreq OPP selected. Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> --- drivers/base/power/main.c | 3 +++ 1 file changed, 3 insertions(+)