From patchwork Tue Jan 17 12:44:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 9520739 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9B4F86043D for ; Tue, 17 Jan 2017 12:46:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8261328544 for ; Tue, 17 Jan 2017 12:46:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 76B8F28548; Tue, 17 Jan 2017 12:46:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6E1728545 for ; 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Tue, 17 Jan 2017 12:45:05 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170117124502eucas1p131b3b424454ee380b0c93899989a51f6~aj8S0oAkU1114911149eucas1p1C; Tue, 17 Jan 2017 12:45:02 +0000 (GMT) X-AuditID: cbfec7ef-f79d26d00000420c-9b-587e11d10567 Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 1A.A5.06687.6021E785; Tue, 17 Jan 2017 12:45:58 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OJX00GNRCQPHB20@eusync2.samsung.com>; Tue, 17 Jan 2017 12:45:02 +0000 (GMT) From: Marek Szyprowski To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Bartlomiej Zolnierkiewicz Subject: [PATCH v2 11/13] pinctrl: samsung: Move retention control from mach-exynos to the pinctrl driver Date: Tue, 17 Jan 2017 13:44:42 +0100 Message-id: <1484657084-26227-12-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1484657084-26227-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsWy7djP87oXBesiDD4f57XYOGM9q8X58xvY Lab8Wc5ksenxNVaLzfP/MFp87j3CaDHj/D4mi7VH7rJbHH7TzmqxatcfRgcuj52z7rJ7bFrV yeZx59oeNo/NS+o9+rasYvT4vEkugC2KyyYlNSezLLVI3y6BK+P+9ZVMBdurK55MbmRrYFye 0cXIySEhYCLx5MN5dghbTOLCvfVsXYxcHEICyxglpl1cwg7hfGaU2PjhOWsXIwdYx/U2Q7ii 5/9nsUI4DUwSP7Y1sICMYhMwlOh62wU2SkSgmVFi5t29YKOYBfqYJD5v3ssIUiUskC1xqu8s mM0ioCqxd89bsEN4BTwlWhsOQx0lJ3Hy2GRWEJsTKP7j53omkEESAv3sEosvtbBA3CQrsekA M0S9i8S9Bx1MELawxKvjW6DmyEh0dhyEivczSjS1akPYMxglzr3lhbCtJQ4fvwi2i1mAT2LS tunMEON5JTrahCBKPCS6dn1lhbAdJfb13WeC+H4Oo8SdaXfYJzDKLGBkWMUoklpanJueWmyo V5yYW1yal66XnJ+7iREY6af/HX+/g/Fpc8ghRgEORiUeXofbNRFCrIllxZW5hxglOJiVRHhf ctdFCPGmJFZWpRblxxeV5qQWH2KU5mBREufdu+BKuJBAemJJanZqakFqEUyWiYNTqoHR6k1c dkh61PW1bP5Hoi6qq7+tWhoRuHCToZZmbu8OrxkZnzi+ndVNrSp7JnpS5Vtq/71JBv8WzDN8 zvjx9SQpqRs+0WwzEozaJ/6uq/oQba3+OUlw+ivnBZu+rlf/uvnZ7a08+ysL5d9u/uk85/6C hO/MEdIV9i7t//f+X+AoeN9B6av3n0MJSizFGYmGWsxFxYkAJB41BfACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsVy+t/xK7psQnURBi+W2VhsnLGe1eL8+Q3s FlP+LGey2PT4GqvF5vl/GC0+9x5htJhxfh+Txdojd9ktDr9pZ7VYtesPowOXx85Zd9k9Nq3q ZPO4c20Pm8fmJfUefVtWMXp83iQXwBblZpORmpiSWqSQmpecn5KZl26rFBripmuhpJCXmJtq qxSh6xsSpKRQlphTCuQZGaABB+cA92AlfbsEt4z711cyFWyvrngyuZGtgXF5RhcjB4eEgInE 9TbDLkZOIFNM4sK99WxdjFwcQgJLGCWWzn7EDOE0MUn0bT7LCFLFJmAo0fW2C6xKRKCZUaJh SS+YwywwgUli5qcGJpAqYYFsiVN9EB0sAqoSe/e8ZQexeQU8JVobDrND7JOTOHlsMiuIzQkU //FzPVivkICHxPn7+1gnMPIuYGRYxSiSWlqcm55bbKhXnJhbXJqXrpecn7uJERj024793LyD 8dLG4EOMAhyMSjy8DrdrIoRYE8uKK3MPMUpwMCuJ8M4VqIsQ4k1JrKxKLcqPLyrNSS0+xGgK dNREZinR5HxgROaVxBuaGJpbGhoZW1iYGxkpifOWfLgSLiSQnliSmp2aWpBaBNPHxMEp1cDY tfpeZ2zCVLfSoh0Wc0R2r45pLRB/b1LxndOIb77CF9GrB++2a89UWWqaHyrX8oF1urLSTen0 b526T72MOPNXnFJKVprprLF61tX3xkbK/f7nxTvrdxquK08yE1xgK6h/aEP230/vbE4fNHq/ 8vm0yt3Ttj+rX72RcbLto4o0xfnMMpI7bSuVWIozEg21mIuKEwH5UxxYkAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170117124502eucas1p131b3b424454ee380b0c93899989a51f6 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170117124502eucas1p131b3b424454ee380b0c93899989a51f6 X-RootMTR: 20170117124502eucas1p131b3b424454ee380b0c93899989a51f6 References: <1484657084-26227-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves pad retention control from PMU driver to Exynos pin controller driver. This helps to avoid possible ordering and logical dependencies between machine, PMU and pin control code. Till now it worked fine only because sys_ops for PMU and pin controller were called in registration order. This is also a preparation for adding new features to Exynos pin controller driver, like runtime power management and suspending individual pin controllers, which might be a part of some power domain. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/suspend.c | 64 -------------- drivers/pinctrl/samsung/pinctrl-exynos.c | 146 +++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+), 64 deletions(-) diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 25e7c5326259..312d3a886e92 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -57,7 +57,6 @@ struct exynos_wkup_irq { struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; - const unsigned int *release_ret_regs; void (*pm_prepare)(void); void (*pm_resume_prepare)(void); @@ -95,47 +94,6 @@ struct exynos_pm_data { { /* sentinel */ }, }; -static const unsigned int exynos_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos3250_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - S5P_PAD_RET_MMC2_OPTION, - S5P_PAD_RET_SPI_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos5420_release_ret_regs[] = { - EXYNOS_PAD_RET_DRAM_OPTION, - EXYNOS_PAD_RET_MAUDIO_OPTION, - EXYNOS_PAD_RET_JTAG_OPTION, - EXYNOS5420_PAD_RET_GPIO_OPTION, - EXYNOS5420_PAD_RET_UART_OPTION, - EXYNOS5420_PAD_RET_MMCA_OPTION, - EXYNOS5420_PAD_RET_MMCB_OPTION, - EXYNOS5420_PAD_RET_MMCC_OPTION, - EXYNOS5420_PAD_RET_HSI_OPTION, - EXYNOS_PAD_RET_EBIA_OPTION, - EXYNOS_PAD_RET_EBIB_OPTION, - EXYNOS5420_PAD_RET_SPI_OPTION, - EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, - REG_TABLE_END, -}; - static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; @@ -441,15 +399,6 @@ static int exynos5420_pm_suspend(void) return 0; } -static void exynos_pm_release_retention(void) -{ - unsigned int i; - - for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) - pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, - pm_data->release_ret_regs[i]); -} - static void exynos_pm_resume(void) { u32 cpuid = read_cpuid_part(); @@ -457,9 +406,6 @@ static void exynos_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -481,9 +427,6 @@ static void exynos3250_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); if (call_firmware_op(resume) == -ENOSYS @@ -521,9 +464,6 @@ static void exynos5420_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); early_wakeup: @@ -636,7 +576,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos3250_pm_data = { .wkup_irq = exynos3250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos3250_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos3250_pm_resume, .pm_prepare = exynos3250_pm_prepare, @@ -646,7 +585,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos4_pm_data = { .wkup_irq = exynos4_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -656,7 +594,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos5250_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -666,7 +603,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), - .release_ret_regs = exynos5420_release_ret_regs, .pm_resume_prepare = exynos5420_prepare_pm_resume, .pm_resume = exynos5420_pm_resume, .pm_suspend = exynos5420_pm_suspend, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 70b94ad10cc1..7beb0d4d2f20 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -28,7 +28,10 @@ #include #include #include +#include #include +#include +#include #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -690,6 +693,55 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) }, }; +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) +{ + if (drvdata->retention_ctrl->refcnt) + atomic_inc(drvdata->retention_ctrl->refcnt); +} + +static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + struct regmap *pmu_regs = drvdata->retention_ctrl->priv; + int i; + + if (drvdata->retention_ctrl->refcnt && + !atomic_dec_and_test(drvdata->retention_ctrl->refcnt)) + return; + + for (i = 0; i < drvdata->retention_ctrl->nr_regs; i++) + regmap_write(pmu_regs, drvdata->retention_ctrl->regs[i], + drvdata->retention_ctrl->value); +} + +static struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct regmap *pmu_regs; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + pmu_regs = exynos_get_pmu_regmap(); + if (IS_ERR(pmu_regs)) + return ERR_CAST(pmu_regs); + + ctrl->priv = pmu_regs; + ctrl->regs = data->regs; + ctrl->nr_regs = data->nr_regs; + ctrl->value = data->value; + ctrl->refcnt = data->refcnt; + ctrl->enable = exynos_retention_enable; + ctrl->disable = exynos_retention_disable; + + return ctrl; +} + /* pin banks of exynos3250 pin-controller 0 */ static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -722,6 +774,30 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) }; /* + * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle + * them all together + */ +static const u32 exynos3250_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + S5P_PAD_RET_MMC2_OPTION, + S5P_PAD_RET_SPI_OPTION, +}; + +static const struct samsung_retention_data exynos3250_retention_data __initconst = { + .regs = exynos3250_retention_regs, + .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes * two gpio/pin-mux/pinconfig controllers. */ @@ -733,6 +809,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos3250_pin_banks1, @@ -741,6 +818,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, }; @@ -793,6 +871,36 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), }; +/* PMU pad retention groups registers for Exynos4 (without audio) */ +static const u32 exynos4_retention_regs[] = { + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, +}; + +static const struct samsung_retention_data exynos4_retention_data __initconst = { + .regs = exynos4_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos4_audio_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, +}; + +static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { + .regs = exynos4_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes * three gpio/pin-mux/pinconfig controllers. @@ -805,6 +913,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4210_pin_banks1, @@ -813,10 +922,12 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4210_pin_banks2, .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .retention_data = &exynos4_audio_retention_data, }, }; @@ -890,6 +1001,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4x12_pin_banks1, @@ -898,6 +1010,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4x12_pin_banks2, @@ -905,6 +1018,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos4x12_pin_banks3, @@ -984,6 +1098,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5250_pin_banks1, @@ -991,6 +1106,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5250_pin_banks2, @@ -1005,6 +1121,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, }; @@ -1231,6 +1348,30 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; +/* PMU pad retention groups registers for Exynos5420 (without audio) */ +static const u32 exynos5420_retention_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, +}; + +static const struct samsung_retention_data exynos5420_retention_data __initconst = { + .regs = exynos5420_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes * four gpio/pin-mux/pinconfig controllers. @@ -1242,26 +1383,31 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5420_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5420_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos5420_pin_banks3, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 4 data */ .pin_banks = exynos5420_pin_banks4, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos4_audio_retention_data, }, };